21 I2C Slave (I2CS)
S1C17602 TECHNICAL MANUAL
EPSON
21-25
I2CS
21.8 Precautions
The I2C slave module operating clock (PCLK) frequency must be set to eight-times or higher than the transfer
rate during data transfer.
When the asynchronous address detection function is enabled, the I2C signals are input without passing through
the noise filter. Therefore, the slave address may not be detected in a high-noise environment.
When the asynchronous address detection function is enabled, data transfer cannot be performed even if the
PCLK frequency is eight-times or higher than the transfer rate. Be sure to disable the asynchronous address
detection function during normal operation.
When the master device of the I2C bus, which has multiple slave devices connected including this IC, starts
communication with another slave device, the I2C slave module of this IC issues NAK in response to the sent
slave address. On the other hand, the selected slave device issues ACK. Therefore, DMS may be set due to a
difference between the output value of this IC and the SDA1 line status. When SELECTED (D1/I2CS_ASTAT
register) is set to 0, you can ignore DMS without a problem even if it is set to 1 as there is a difference in the
response code (ACK/NAK) from the selected slave device.
When the I2C slave is placed into asynchronous address detection mode, a DMS does not occur as in the
condition above.
When setting the first transmit data after this module has been selected as the slave device, follow the precautions
described below.
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after TXEMP
has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP has
been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data
to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary.
When the clock stretch function is enabled
The master device is placed into wait status by the clock stretch function, so transmit data can be written
after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it will be sent
immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_TRNS register using
TBUF_CLR (D8/I2CS_CTL register) before this module is selected as the slave device. The I2CS_TRNS
register is cleared by writing 1 to TBUF_CLR then writing 0 to it.
It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TXEMP has
been set.
When the clock stretch function has been disabled, transmit data/receive data must be written/read within the
time shown below.
During data transmission:
Within 7 cycles of the I2C slave clock (SCL1) after TXEMP is set (a transmit interrupt occurs)
(See the precaution above for the first transmit data after slave selection.)
During data reception:
Within 7 cycles of the I2C slave clock (SCL1) after RXRDY is set (a receive interrupt occurs)
To return NAK, NAK_ANS should be set within this period.