6 Interrupt Controller
S1C17602 TECHNICAL MANUAL
EPSON
6-3
6.3 Maskable Interrupt Control
6.3.1 Peripheral Module Interrupt Control Bit
The peripheral module causing the interrupt includes interrupt enable bits and interrupt flags for each interrupt
cause. Setting the interrupt enable bit to 1 (interrupt permitted) sets the interrupt flag to 1, depending on the cause
of the interrupt. The flag state is sent to the ITC as an interrupt request signal, generating an interrupt request to
the S1C17 core. The corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are
not desired. In this case, the interrupt flag will not be set to 1, even if the interrupt cause occurs, and the interrupt
request signal will not be activated to the ITC.
Interrupt flags set to 1 must be reset within the interrupt processing routine after the interrupt has occurred. The ITC
will generate the same interrupt again once the interrupt processing routine has been ended by the reti instruction
with the interrupt flag still set to 1, since it detects interrupt requests using the signal level.
For specific information on interrupt causes, interrupt flags, and interrupt enable bits, refer to the individual
peripheral module descriptions.
6.3.2 ITC Interrupt Request Processing
On receiving an interrupt signal from a peripheral module, the ITC sends interrupt request, interrupt level, and
vector number signals to the S1C17 core.
Vector numbers are determined by the ITC internal hardware for each interrupt cause, as shown in Table 6.2.1.
The interrupt level is a value used by the S1C17 core to compare with the IL bit (PSR). This interrupt level is used
in the S1C17 core to prohibit subsequently occurring interrupts with the same or lower level. (See section 6.3.3.)
The default ITC settings are level 0 for all maskable interrupts. Interrupt requests are not accepted by the S1C17
core if the level is 0.
The ITC includes control bits for selecting the interrupt level, and these can be set to between 0 (low) and 7 (high)
interrupt levels for each interrupt type.
Table 6.3.2.1: Interrupt level setting bits
Hardware interrupt
Interrupt level setting bit
Register address
P0 port interrupt
ILV0[2:0] (D[2:0]/ITC_LV0 register)
0x4306
P1 port interrupt
ILV1[2:0] (D[10:8]/ITC_LV0 register)
0x4306
Stopwatch timer interrupt
ILV2[2:0] (D[2:0]/ITC_LV1 register)
0x4308
Clock timer interrupt
ILV3[2:0] (D[10:8]/ITC_LV1 register)
0x4308
8-bit OSC1 timer interrupt
ILV4[2:0] (D[2:0]/ITC_LV2 register)
0x430a
SVD interrupt
ILV5[2:0] (D[10:8]/ITC_LV2 register)
0x430a
LCD interrupt
ILV6[2:0] (D[2:0]/ITC_LV3 register)
0x430c
PWM timer Ch.0 interrupt
ILV7[2:0] (D[10:8]/ITC_LV3 register)
0x430c
8-bit timer Ch.0/Ch.1 interrupt
ILV8[2:0] (D[2:0]/ITC_LV4 register)
0x430e
16-bit timer Ch.0 interrupt
ILV9[2:0] (D[10:8]/ITC_LV4 register)
0x430e
16-bit timer Ch.1 interrupt
ILV10[2:0] (D[2:0]/ITC_LV5 register)
0x4310
16-bit timer Ch.2 interrupt
ILV11[2:0] (D[10:8]/ITC_LV5 register)
0x4310
UART Ch.0 interrupt
ILV12[2:0] (D[2:0]/ITC_LV6 register)
0x4312
UART Ch.0/I2C (slave) interrupt
ILV13[2:0] (D[10:8]/ITC_LV6 register)
0x4312
SPI interrupt
ILV14[2:0] (D[2:0]/ITC_LV7 register)
0x4314
I2C (master) interrupt
ILV15[2:0] (D[10:8]/ITC_LV7 register)
0x4314
Remote controller interrupt
ILV16[2:0] (D[2:0]/ITC_LV8 register)
0x4316
reserved
ILV17[2:0] (D[10:8]/ITC_LV8 register)
0x4316
A/D Conveter interrupt
ILV18[2:0] (D[2:0]/ITC_LV9 register)
0x4318
R/F Conveter interrupt
ILV19[2:0] (D[10:8]/ITC_LV9 register)
0x4318
ITC