3 Memory Map and Bus Control
3-4
EPSON
S1C17602 TECHNICAL MANUAL
0x17ffc–0x17ffe: Flash Protect Bits
Address
Bit
Function
Setting
Init. R/W
Remarks
0x17ffc
(16 bits)
D15–4 reserved
–
D3
Flash write-protect bit for 0x14000–0x17fff
1 Writable
0 Protected
1 R/W
D2
Flash write-protect bit for 0x10000–0x13fff
1 Writable
0 Protected
1 R/W
D1
Flash write-protect bit for 0x0c000–0x0ffff
1 Writable
0 Protected
1 R/W
D0
Flash write-protect bit for 0x08000–0x0bfff
1 Writable
0 Protected
1 R/W
0x17ffe
(16 bits)
D15–4 reserved
–
D3
Flash data-read-protect bit for 0x14000–0x17fff 1 Readable
0 Protected
1 R/W
D2
Flash data-read-protect bit for 0x10000–0x13fff 1 Readable
0 Protected
1 R/W
D1
Flash data-read-protect bit for 0x0c000–0x0ffff
1 Readable
0 Protected
1 R/W
D0
reserved
1
1 R/W Set to 1
Note: Do not place the area set for data read-protect in the .data or .rodata sections.
D0 of 0x17ffe must always be set to 1. The program cannot be booted if this is set to 0.
3.2.4 Flash Controller Access Control
The S1C17602 internal flash memory is accessed via a dedicated flash controller. The MISC register is used for
setting access to this controller.
Flash controller read access cycle settings
Set the optimum read access cycles using FLCYC[2:0] (D[2:0]/MISC_FL register) to suit the CCLK frequency
to ensure that data is read correctly from the flash memory.
0x5320: FLASHC/SRAMC Control Register (MISC_FL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC/
SRAMC Control
Register
(MISC_FL)
0x5320
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 FLCYC[2:0] FLASHC read access cycle
FLCYC[2:0]
Read cycle
0x3 R/W
0x7–0x5
0x4
0x3
0x2
0x1
0x0
reserved
1 cycles
5 cycles
4 cycles
3 cycles
2 cycles
D[2:0]
FLCYC[2:0]: FLASHC Read Access Cycle Setup Bits
Sets the number of read access cycles for the flash controller.
Table 3.2.4.1: Flash controller read access cycle settings
FLCYC[2:0]
Read access cycles
CCLK frequency
0x7 to 0x5
Reserved
–
0x4
1 cycle
8.2 MHz max.
0x3
5 cycles
8.2 MHz max.
0x2
4 cycles
8.2 MHz max.
0x1
3 cycles
8.2 MHz max.
0x0
2 cycles
8.2 MHz max.
(Default: 0x3)
Note: Do not set the read access cycles to a value exceeding the CCLK maximum permissible
frequency. This will cause malfunctions.
Set FLCYC[2:0]=0x4 in order to maximize the performance.