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16 Stopwatch Timer (SWT)
16-6
EPSON
S1C17602 TECHNICAL MANUAL
16.6 Stopwatch Timer Interrupts
The SWT module includes functions for generating the following three kinds of interrupts:
100 Hz interrupt
10 Hz interrupt
1 Hz interrupt
The SWT module outputs a single interrupt signal shared by the above three interrupt factors to the interrupt
controller (ITC). The interrupt flag within the SWT module should be read to identify the interrupt factor that
occurred.
100 Hz, 10 Hz, 1 Hz interrupts
Generated at the 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges,
these interrupt requests set the following interrupt flags in the SWT module to 1.
SIF1:
1 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D2/0x5023)
SIF10:
10 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D1/0x5023)
SIF100: 100 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D0/0x5023)
To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the
interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for
this factor will not be sent to the ITC.
SIE1:
1 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D2/0x5022)
SIE10:
10 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D1/0x5022)
SIE100: 100 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D0/0x5022)
The SWT module outputs an interrupt request to the ITC if the SIF* is set to 1. This interrupt request signal
generates an interrupt if the ITC and S1C17 core interrupt conditions are met.
Check the frequency of a stopwatch timer interrupt by reading SIF* as part of the stopwatch timer interrupt
processing routine.
Note: To prevent interrupt recurrences, the SWT module interrupt flag SIF*must be reset within
the interrupt processing routine following a stopwatch timer interrupt.
To prevent generating unnecessary interrupts, reset the corresponding SIF* before
permitting stopwatch timer interrupt from SIE*.
Interrupt vectors
The stopwatch timer interrupt vector numbers and vector addresses are listed below.
Vector number: 6 (0x06)
Vector address: TTBR + 0x18
Other interrupt settings
The ITC allows the priority of stopwatch timer interrupts to be set between level 0 (the default value) and level
7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit
must be set to 1.
For more information on interrupt processing, see “6 Interrupt Controller (ITC).”