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7 Oscillator Circuit (OSC)
7-2
EPSON
S1C17602 TECHNICAL MANUAL
7.2 IOSC Oscillator Circuit
The IOSC oscillator circuit allows the high-speed start of oscillation without any external components. The
oscillation starts when the power is turned on, and generates the clock for S1C17 and peripheral circuit during
initialization.
IOSC oscillation on/off
The IOSC oscillator circuit stops oscillating if IOSCEN (D2/OSC_CTL register) is set to 0 and begins
oscillating if set to 1. The IOSC oscillator circuit stops oscillating even in SLEEP mode.
IOSCEN: IOSC Enable Bit in the Oscillation Control (OSC_CTL) Register (D2/0x5061)
Following initial resetting, IOSCEN is set to 1, and the IOSC oscillator circuit is on. Since the IOSC clock is
used as the system clock, the S1C17 core begins operating using the IOSC clock.
The S1C17602 also contains an OSC3 oscillator circuit for high-speed clock generation. Selection of IOSC or
OSC3 as the high-speed clock can occur after startup. For specific information on selecting the clock, refer to “7.5
Clock Switching.”
Stabilization wait time when IOSC oscillation begins
When using the IOSC clock, the IOSC oscillator circuit incorporates an oscillation stabilization wait timer to
prevent malfunctions due to unstable clock operations when IOSC oscillation begins—e.g., when waking from
SLEEP, or when the IOSC oscillation circuit is turned on via software. The IOSC clock is not fed to the system
until the time set for this timer has elapsed.
One from the four different oscillation stabilization wait times using IOSCWT[1:0](D[7:6]/OSC_CTL register
can be selected.
IOSCWT[1:0]: IOSC Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[7:6]/0x5061)
Table 7.2.1: IOSC oscillation stabilization wait time settings
IOSCWT[1:0]
Oscillation stabilization wait time
0x3
8 cycles
0x2
16 cycles
0x1
32 cycles
0x0
64 cycles
(Default: 0x0)
This being set to 64 cycles (IOSC clock) after initial resetting, the CPU will not start operating after release of
the reset until the time defined in the following elapses.
During initialization, CPU operation start time =< IOSC oscillation start time (max.) + IOSC oscillation
stabilization wait time (64 cycles)
If power supply voltage VDD is fully stable, the oscillation stabilization wait time can be shortened by setting
IOSCWT[1:0]=0x3.
IOSC clock system supply wait time =< IOSC oscillation start time (max.) + IOSC oscillation
stabilization wait time.