10 Input/Output Port (P)
S1C17602 TECHNICAL MANUAL
EPSON
10-7
IOPort
10.6 P0 and P1 Port Chattering Filter Function
The P0 and P1 port include a chattering filter circuit for key entry, which you can select to use or not use (and for
which you can select a verification time if used) individually for the four P0[3:0] and P0[7:4], P1
ports using PxCF1[2:0] (D[2:0]/Px_CHAT register), PxCF2[2:0] (D[6:4]/Px_CHAT register).
P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[2:0]/0x5208)
P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[6:4]/0x5208)
P1CF1[2:0]: P1[3:0] Chattering Filter Time Select Bits in the P1 Port Chattering Filter Control (P1_CHAT)
Register (D[2:0]/0x5218)
P1CF2[2:0]: P1[7:4] Chattering Filter Time Select Bits in the P1 Port Chattering Filter Control (P1_CHAT)
Register (D[6:4]/0x5218)
Table 10.6.1: Chattering filter function settings
PxCF1[2:0]/PxCF2[2:0]
Verification time *
0x7
16384/fPCLK (8ms)
0x6
8192/fPCLK (4ms)
0x5
4096/fPCLK (2ms)
0x4
2048/fPCLK (1ms)
0x3
1024/fPCLK (512s)
0x2
512/fPCLK (256s)
0x1
256/fPCLK (128s)
0x0
No verification time
(Off)
(Default: 0x0, *when HSCLK = 2 MHz and PCLK = HSCLK)
Note: The chattering filter verification time refers to the maximum pulse width that can be filtered.
Generating an input interrupt requires a minimum input time of the verification time and a
maximum input time of twice the verification time.
Input interrupts will not be accepted for a transition into SLEEP mode with the chattering
filter left on. The chattering filter should be set off (no verification time) before executing the
slp instruction.
P0/P1 port interrupts must be blocked when Px_CHAT register (0x5208/0x5218) settings are
being changed. Changing the setting while interrupts are permitted may generate inadvertent
P0/P1 interrupts.
A phenomenon may occur in which the internal signal oscillates due to the time elapsed until
the signal reaches the threshold value if the input signal rise-up/drop-off time is delayed.
Since input interrupts will malfunction under these conditions, the input signal rise-up/drop-
off time should normally be set to 25 ns or less.