21. Multi-Function Timer Pulse Unit 2 (MTU2A)
21.2.9
Timer A/D Converter Start Request Control Register (TADCR)
Note 1. TADCR must not be accessed in 8-bit units; it should be accessed in 16-bit units.
Note 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to
0 or the skipping count set bits (T3ACOR and T4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control
register (TADCR) to 0).
Note 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued.
Note 4. Do not initialize b6 to b0 to 1 when complementary PWM mode is not selected.
The MTU2A has one TADCR each for MTU4.
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether
to link A/D converter start requests with interrupt skipping operation.
Address(es): MTU4.TADCR 0008 8640h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
BF[1:0]
————
——
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
Value after reset:
00000
000
Note 1. Do not set to 1 when complementary PWM mode is not selected.
Bit
Symbol
Bit Name
Description
R/W
b0
ITB4VE
TCIV4 Interrupt Skipping Link Enable
0: TCI4V interrupt skipping is not linked
1: TCI4V interrupt skipping is linked
R/W
b1
ITB3AE
TGIA3 Interrupt Skipping Link Enable
0: TGI3A interrupt skipping is not linked
1: TGI3A interrupt skipping is linked
R/W
b2
ITA4VE
TCIV4 Interrupt Skipping Link Enable
0: TCI4V interrupt skipping is not linked
1: TCI4V interrupt skipping is linked
R/W
b3
ITA3AE
TGIA3 Interrupt Skipping Link Enable
0: TGI3A interrupt skipping is not linked
1: TGI3A interrupt skipping is linked
R/W
b4
DT4BE
Down-Count TRG4BN Enable
0: A/D converter start requests (TRG4BN) disabled
during MTU4.TCNT down-count operation
1: A/D converter start requests (TRG4BN) enabled
during MTU4.TCNT down-count operation
R/W
b5
UT4BE
Up-Count TRG4BN Enable
0: A/D converter start requests (TRG4BN) disabled
during MTU4.TCNT up-count operation
1: A/D converter start requests (TRG4BN) enabled
during MTU4.TCNT up-count operation
R/W
b6
DT4AE
Down-Count TRG4AN Enable
0: A/D converter start requests (TRG4AN) disabled
during MTU4.TCNT down-count operation
1: A/D converter start requests (TRG4AN) enabled
during MTU4.TCNT down-count operation
R/W
b7
UT4AE
Up-Count TRG4AN Enable
0: A/D converter start requests (TRG4AN) disabled
during MTU4.TCNT up-count operation
1: A/D converter start requests (TRG4AN) enabled
during MTU4.TCNT up-count operation
R/W
b13 to b8
—
Reserved
These bits are read as 0. The write value should be 0. R/W
b15, b14
BF[1:0]
MTU4.TADCOBRA/B Transfer Timing Select
R/W