29. I2C Bus Interface (RIIC)
29.3.4
Master Receive Operation
In master receive operation, the RIIC as a master device outputs the SCL (clock) signal, receives data from the slave
device, and returns acknowledgements. Since the RIIC must start by sending a slave address to the corresponding slave
device, this part of the procedure is performed in master transmit mode, but the subsequent steps are in master receive
mode.
operations in master reception.
The following describes the procedure and operations for master reception.
(1) Set the IICRST bit in ICCR1 to 1 (internal reset) and then clear the IICRST bit to 0 (canceling reset) with the ICE
bit in ICCR1 cleared to 0 (disabling the interface). This initializes the internal state and the various flags of ICSR1.
After that, set registers SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL (y = 0 to 2), and set the other
registers as necessary (for initial settings of the RIIC, see
Figure 29.5). When the necessary register settings have
been completed, set the ICE bit to 1 (to enable transfer). This step is not necessary if initialization of the RIIC has
already been completed.
(2) Read the BBSY flag in ICCR2 to check that the bus is open, and then set the ST bit in ICCR2 to 1 (start condition
issuance request). Upon receiving the request, the RIIC issues a start condition. When the RIIC detects the start
condition, the BBSY flag and the START flag in ICSR2 are automatically set to 1 and the ST bit is automatically
cleared to 0. At this time, if the start condition is detected and the levels for the SDA output and the levels on the
SDA0 line have matched while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by
the ST bit has been successfully completed, and the MST and TRS bits in ICCR2 are automatically set to 1, placing
the RIIC in master transmit mode. The TDRE flag in ICSR2 is also automatically set to 1 in response to setting of
the TRS bit to 1.
(3) Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the first byte indicates the slave
address and value of the R/W# bit) to ICDRT. Once the data for transmission are written to ICDRT, the TDRE flag
is automatically cleared to 0, the data are transferred from ICDRT to ICDRS, and the TDRE flag is again set to 1.
Once the byte containing the slave address and R/W# bit has been transmitted, the value of the ICCR2.TRS bit is
automatically updated to select transmit or receive mode in accord with the value of the transmitted R/W# bit. If the
value of the R/W# bit was 1, the TRS bit is cleared to 0 on the rising edge of the ninth cycle of SCL0 (the clock
signal), placing the RIIC in master receive mode. At this time, the TDRE flag is automatically cleared to 0 and the
ICSR2.RDRF flag is automatically set to 1.
Since the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was
an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, and then issue a restart condition. After that, transmitting 1111 0b, the two higher-order bits of the slave
address, and the R bit places the RIIC in master receive mode.
(4) Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1; this makes the RIIC start output of the
SCL (clock) signal and start data reception.
(5) After 1 byte of data has been received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the eighth or ninth
cycle of SCL clock (the clock signal) as selected by the RDRFS bit in ICMR3. Reading out ICDRR at this time will
produce the received data, and the RDRF flag is automatically cleared to 0 at the same time. Furthermore, the value
of the acknowledgement field received during the ninth cycle of SCL clock is returned as the value set in the
ACKBT bit of ICMR3. Furthermore, if the next byte to be received is the next to last byte, set the ICMR3.WAIT bit
to 1 (for wait insertion) before reading the ICDRR (containing the second byte from last). As well as enabling
NACK output even in the case of delays in processing to set the ICMR3.ACKBT bit to 1 (NACK) in step (6), due to
other interrupts etc., this fixes the SCL0 line to the low level on the rising edge of the ninth clock cycle in reception
of the last byte, so the state is such that issuing a stop condition is possible.
(6) When the ICMR3.RDRFS bit is 0 and the slave device must be notified that it is to end transfer for data reception
after transfer of the next (final) byte, set the ACKBT bit in ICMR3 to 1 (NACK).