11. Low Power Consumption
11.6.3
Software Standby Mode
11.6.3.1
Transition to Software Standby Mode
When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1 and the DPSBYCR.DPSBY bit cleared to 0, a
transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions, and all the oscillator
functions stop. However, the contents of the CPU internal registers, on-chip RAM data, on-chip peripheral functions, and
the states of the I/O ports are retained. Software standby mode allows significant reduction in power consumption
because the oscillator stops in this mode.
Further reduction of power consumption is possible by using the FHSSBYCR register. In standby mode, internal power
supply to the on-chip ROM is stopped when the FHSSBYCR.SOFTCUT0 bit is set to 1, and power supply to the on-chip
high-speed oscillator is stopped when the FHSSBYCR.SOFTCUT1 bit is set to 1. When the FHSSBYCR.SOFTCUT2
bit is set to 1, power supply to the voltage detection circuit (LVD) is stopped and the power consumption reduction
function by the power-on reset circuit (POR) is enabled. This varies the voltage detection characteristic of the POR. For
details, refer to section 41, Electrical Characteristics.
Clear the DMAST.DMST bit of the DMACA and the DTCST.DTCST bit of the DTC to 0 before executing the WAIT
instruction.
When the WDT is used, the WDT stops counting when software standby mode is entered because the oscillator stops.
Counting by the IWDT stops if a transition to software standby mode is made while the IWDT is being used in auto-start
mode and the OFS0.IWDTSLCSTP bit is 1. In the same way, counting by the IWDT stops if a transition to software
standby mode is made while the IWDT is being used in register start mode and the SLCSTP bit in IWDTCSTPR is 1.
Furthermore, counting by the IWDT continues if a transition to software standby mode is made while the IWDT is being
used in auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by the IWDT continues through transitions to
low-power-consumption modes). In the same way, counting by the IWDT continues if a transition to software standby
mode is made while the IWDT is being used in register start mode and the SLCSTP bit in IWDTCSTPR is 0.
When the oscillation stop detection function is enabled (OSTDCR.OSTDE = 1), software standby mode cannot be
entered. To make a transition to software standby mode, issue a WAIT instruction after disabling the oscillation stop
detection function (OSTDCR.OSTDE = 0).
To use software standby mode, make the following settings and then execute a WAIT instruction.
(1) Clear the PSW.I bit
*1 of the CPU to 0.
(2) Set the interrupt destination to be used for recovery from software standby mode to the CPU.
(3) Set the
priority*2 of the interrupt to be used for recovery from software standby mode to a level higher than the
setting of the PSW.IPL[3:0] bits
*1 of the CPU.
(4) Set the IERm.IENj bit
*2 for the interrupt to be used for recovery from software standby mode to 1.
(5) For the last I/O register to which writing proceeded, read the register to confirm that the value written has been
reflected.
(6) Execute a WAIT instruction (executing a WAIT instruction causes automatic setting of the PSW.I
bit*1 of the CPU
to 1).
Note 1.
Note 2.