32. 12-Bit A/D Converter (S12AD)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
32.2.6
A/D Control Register (ADCSR)
Note 1. Starting A/D conversion using an external pin (asynchronous trigger)
If 1 is written to both the TRGE and EXTRG bits in ADCSR when a high-level signal is input to the external pin (ADTRG0#), and
then if the ADTRG0# signal is driven low, the falling edge of ADTRG0# is detected and the scan conversion process is started.
In this case, the pulse width of the low-level input must be at least 1.5 PCLK clock cycles.
ADCSR sets duplication of the A/D conversion data, double trigger mode, A/D conversion start trigger; enables/disables
scan end interrupt; selects the scan mode; and starts or stops A/D conversion.
DBLANS[4:0] Bits (A/D Conversion Data Duplication Channel Select)
The DBLANS[4:0] bits select one of the channels for A/D conversion data duplication in double trigger mode. The A/D
conversion results of the analog input of the selected channel are stored into A/D data register y when conversion is
started by the first trigger, and into the A/D data duplication register when started by the second trigger.
Table 32.5shows the relationship between the DBLANS bit settings and selected duplication channel. A/D-converted value
addition mode with double trigger mode can be set by selecting the channel selected by the DBLANS[4:0] bits using the
ADADS register. If double trigger mode is selected, the channel selected by the ADANSA register is invalid, and the
channel selected by the DBLANS [4:0] bits is subjected to A/D conversion instead. When converting analog inputs of
channels, temperature sensor output or internal reference voltage should not be selected for A/D conversion.
The DBLANS[4:0] bits should be set while the ADST bit is 0 (they should not be set simultaneously when 1 is written to
the ADST bit.)
Address: 0008 9000h
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
ADST
ADCS[1:0]
ADIE
—
TRGE EXTRG DBLE GBADI
E
—
DBLANS[4:0]
Value after reset:
00000
0000000
0000
Bit
Symbol
Bit Name
Description
R/W
b4 to b0
A/D Conversion Data
Duplication Channel
Select
Select one of 16 analog input channels for A/D conversion data
duplication. These bits are valid only in double trigger mode.
R/W
b5
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b6
Group B Scan End
Interrupt Enable
0: Disables GBADI interrupt generation upon group B scan
completion.
1: Enables GBADI interrupt generation upon group B scan completion.
R/W
b7
Double Trigger Mode
Select
0: Deselects double trigger mode.
1: Selects double trigger mode.
R/W
b8
Trigger Select*1
0: A/D conversion is started by the synchronous trigger (MTU, ELC, or
temperature sensor).
1: A/D conversion is started by the asynchronous trigger (ADTRG0#).
R/W
b9
Trigger Start Enable
0: Disables A/D conversion to be started by the synchronous or
asynchronous trigger.
1: Enables A/D conversion to be started by the synchronous or
asynchronous trigger.
R/W
b10, b11
—
Reserved
This bit is read as 0. The write value should be 0.
R/W
b12
Scan End Interrupt
Enable
0: Disables S12ADI0 interrupt generation upon scan completion.
1: Enables S12ADI0 interrupt generation upon scan completion.
R/W
b14, b13
Scan Mode Select
b14 b13
0 0: Single-cycle scan mode
0 1: Group scan mode
1 0: Continuous scan mode
1 1: Setting prohibited
R/W
b15
A/D Conversion Start
0: Stops A/D conversion process.
1: Starts A/D conversion process.
R/W