28. Serial Communications Interface (SCIc, SCId)
x: Don’t care
Note 1. Writable only when TE = 0 and RE = 0.
Note 2. A 1 can be written only when TE = 0 and RE = 0, while the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written in
TE and RE. While the SMR.CM bit is 0, writing is enabled under any condition.
SCR is a register that controls the SCI transfer operations and selects the transfer clock source.
CKE[1:0] Bits (Clock Enable)
These bits select the clock source and SCKn pin function.
The combination of the settings of these bits and of the SEMR.ACS0 bit sets the internal TMR clock.
TEIE Bit (Transmit End Interrupt Enable)
Enables or disables a TEI interrupt request.
A TEI interrupt request is disabled by clearing the TEIE bit to 0.
In simple I2C mode (when the IICM bit in SIMR is 1), the TEI is allocated to the interrupt on completion of issuing a
start, restart, or stop condition (STI). In this case, the TEIE bit can be used to enable or disable the STI.
MPIE Bit (Multi-Processor Interrupt Enable)
When this bit is set to 1 and the data with the multi-processor bit set to 0 is received, the data is not read and setting the
status flags ORER and FER in SSR to 1 is disabled. When the data with the multi-processor bit set to 1 is received, the
When the receive data includes the MPB bit is SSR set to 0, the receive data is not transferred from the RSR to the RDR,
a receive error is not detected, and setting the flags ORER and FER to 1 is disabled.
When the receive data includes the MPB bit set to 1, the MPB bit is set to 1, the MPIE bit is automatically cleared to 0,
the RXI and ERI interrupt requests are enabled (if the RIE bit in SCR is set to 1), and setting the flags ORER and FER to
1 is enabled.
MPIE should be set to 0 if multi-processor communications function is not to be used.
RE Bit (Receive Enable)
Enables or disables serial reception.
When this bit is set to 1, serial reception is started by detecting the start bit in asynchronous mode or the synchronous
clock input in clock synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate
the reception format.
Even if reception is halted by clearing the RE bit to 0, the ORER, FER, and PER flags in SSR are not affected and the
previous value is retained.
TE Bit (Transmit Enable)
Enables or disables serial transmission.
When this bit is set to 1, serial transmission is started by writing transmit data to TDR. Note that SMR should be set prior
to setting the TE bit to 1 in order to designate the transmission format.
b4
Receive Enable
0: Serial reception is disabled
1: Serial reception is enabled
b5
Transmit Enable
0: Serial transmission is disabled
1: Serial transmission is enabled
b6
Receive Interrupt Enable
0: RXI and ERI interrupt requests are disabled
1: RXI and ERI interrupt requests are enabled
R/W
b7
Transmit Interrupt Enable
0: A TXI interrupt request is disabled
1: A TXI interrupt request is enabled
R/W
Bit
Symbol
Bit Name
Description
R/W