27. Independent Watchdog Timer (IWDT)
27.3.3
Refresh Operation
The down-counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then
FFh to the IWDT refresh register (IWDTRR). If a value other than FFh is written after 00h, the down-counter is not
refreshed. After such invalid writing, correct refreshing is performed by again writing 00h and then FFh to the IWDT
refresh register (IWDTRR).
When writing is done in the order of 00h (first time) → 00h (second time), and if FFh is written after that, the writing
order 00h → FFh is satisfied; writing 00h (n–1-th time) → 00h (n–th time) → FFh is valid and correct refreshing will be
done. Even when the first value written before 00h is not 00h, correct refreshing will be done if the operation contains the
set of writing 00h → FFh. Moreover, even if a register other than IWDTRR is accessed or IWDTRR is read between
writing 00h and writing FFh to IWDTRR, correct refreshing will be done.
[Sample sequences of writing that are valid for refreshing the counter]
00h→FFh
00h (n–1-th time) →00h (n-th time) →FFh
00h→access to another register or read from IWDTRR→FFh
[Sample sequences of writing that are not valid for refreshing the counter]
23h (a value other than 00h) →FFh
00h→54h (a value other than FFh)
00h→AAh (00h and a value other than FFh) →FFh
Even when 00h is written to IWDTRR outside the refresh-permitted period, if FFh is written to IWDTRR in the refresh-
permitted period, the writing sequence is valid and refreshing will be done.
After FFh is written to the IWDTRR register, refreshing the down-counter requires up to four cycles of the signal for
counting (the clock division ratio selection (the clock division ratio selection (IWDTCR.CKS[3:0]) bits determine how
many cycles of the IWDT-dedicated low-speed clock (IWDTCLK) make up one cycle for counting). Therefore, writing
FFh to the IWDTRR should be completed four-count cycles before the end position of the refresh-permitted period or a
counter underflow. The value of the down-counter can be checked by the counter bits (IWDTSR.CNTVAL[13:0]).
[Sample refreshing timings]
When the window start position is set to 1FFFh, even if 00h is written to IWDTRR before 1FFFh is reached (2002h,
for example), refreshing is done if FFh is written to IWDTRR after the value of the IWDTSR.CNTVAL[13:0] bits
has reached 1FFFh.
When the window end position is set to 1FFFh, refreshing is done if 2003h (four-count cycles before 1FFFh) or a
greater value is read from the IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to IWDTRR.
When the refresh-permitted period continues until count 0000h, refreshing can be done immediately before an
underflow. In this case, if 0003h (four-count cycles before an underflow) or a greater value is read from the
IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to IWDTRR, no underflow occurs and
refreshing is done.