29. I2C Bus Interface (RIIC)
SDAO Bit (SDA Output Control)
This bit controls the output level of the SDA0 pin. This bit also monitors the output state of the SDA0 pin.
SCLO Bit (SCL Output Control)
This bit controls the output level of the SCL0 pin. This bit also monitors the output state of the SCL0 pin.
SOWP Bit (SCLO/SDAO Write Protect)
This bit controls the modification of the SCLO and SDAO bits.
CLO Bit (Extra SCL Clock Cycle Output)
This bit is used to output an extra SCL clock cycle for debugging or error processing.
Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error.
IICRST Bit (I2C Bus Interface Internal Reset)
This bit is used to reset the internal states of the RIIC.
Setting this bit to 1 initiates an RIIC reset or internal reset.
Whether an RIIC reset or internal reset is initiated is determined according to the combination with the ICE bit.
Table29.4 lists the resets of the RIIC.
The RIIC reset resets all registers including the BBSY flag in ICCR2 and internal states of the RIIC, and the internal
reset resets the bit counter (BC[2:0] bits in ICMR1), the I2C bus shift register (ICDRS), and the I2C bus status registers
(ICSR1 and ICSR2) as well as the internal states of the RIIC. For the reset conditions for each register, see
sectionAn internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states
of the RIIC without initializing the port settings and the control and setting registers of the RIIC when the bus or RIIC
hangs up due to a communication error.
If the RIIC hangs up in a low level output state, resetting the internal states cancels the low level output state and releases
the bus with the SCL0 pin and SDA0 pin at a high impedance.
Note: If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the
master device in slave mode, the states may become different between the slave device and the master device
(due to the difference in the bit counter information). For this reason, do not initiate an internal reset in slave
mode, but initiate restoration processing from the master device. If an internal reset is necessary because the
RIIC hangs up with the SCL0 line in a low level output state in slave mode, initiate an internal reset and then issue
a restart condition from the master device or resume communication from the start condition issuance after
issuing a stop condition. If communication is restarted by initiating a reset solely in the slave device without
issuing a start condition or restart condition from the master device, synchronization will be lost because the
master and slave devices operate asynchronously.
Table 29.4
RIIC Resets
IICRST
ICE
State
Specifications
1
0
RIIC reset
Resets all registers and internal states of the RIIC.
1
Internal reset
Reset the BC[2:0] bits in ICMR1, and the ICSR1, ICSR2, ICDRS registers and the
internal states of the RIIC.