21. Multi-Function Timer Pulse Unit 2 (MTU2A)
21.2.31
Noise Filter Control Registers (NFCR)
NFCR (MTU0 to MTU4)
Note 1. These bits are reserved in the NFCRs for MTU1 and MTU2. These bits are read as 0, and writing to them is not possible.
MTUn.NFCR is 8-bit readable and writable register (n = 0 to 4). These registers control enabling and disabling of the
noise filters for the MTIOCnm (n = 0 to 4; m = A to D) pins and sets the sampling clocks for the noise filters.
NFAEN Bit (Noise Filter A Enable)
This bit disables or enables the noise filter for input from the MTIOCnA pin. Since unexpected edges may be internally
generated when the value of NFAEN is changed, select the output compare function in the timer I/O control register and
set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before changing the value.
NFBEN Bit (Noise Filter B Enable)
This bit disables or enables the noise filter for input from the MTIOCnB pin. Since unexpected edges may be internally
generated when the value of NFBEN is changed, select the output compare function in the timer I/O control register and
set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before changing the value.
NFCEN Bit (Noise Filter C Enable)
This bit disables or enables the noise filter for input from the MTIOCnC pin. Since unexpected edges may be internally
generated when the value of NFCEN is changed, select the output compare function in the timer I/O control register and
set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before changing the value.
NFDEN Bit (Noise Filter D Enable)
This bit disables or enables the noise filter for input from the MTIOCnD pin. Since unexpected edges may be internally
generated when the value of NFDEN is changed, select the output compare function in the timer I/O control register and
set the TMDR.MD[3:0] bits to a value other than that for normal mode (0000b) before changing the value.
Address(es): MTU0.NFCR 0008 8690h, MTU1.NFCR 0008 8691h, MTU2.NFCR 0008 8692h,
MTU3.NFCR 0008 8693h, MTU4.NFCR 0008 8694h
b7
b6
b5
b4
b3
b2
b1
b0
—
NFCS[1:0]
NFDEN NFCEN NFBEN NFAEN
Value after reset:
00000
000
Bit
Symbol
Bit Name
Description
R/W
b0
NFAEN
Noise Filter A Enable Bit
0: The noise filter for the MTIOCnA pin is disabled.
1: The noise filter for the MTIOCnA pin is enabled.
R/W
b1
NFBEN
Noise Filter B Enable Bit
0: The noise filter for the MTIOCnB pin is disabled.
1: The noise filter for the MTIOCnB pin is enabled.
R/W
b2
NFCEN
Noise Filter C Enable Bit
0: The noise filter for the MTIOCnC pin is disabled.
1: The noise filter for the MTIOCnC pin is enabled.
R/(W)
b3
NFDEN
Noise Filter D Enable Bit
0: The noise filter for the MTIOCnD pin is disabled.
1: The noise filter for the MTIOCnD pin is enabled.
R/(W)
b5, b4
NFCS[1:0]
Noise Filter Clock Select
00: PCLK/1
01: PCLK/8
10: PCLK/32
11: PCLK/Source that drives counting
R/W
b7, b6
—
Reserved
These bits are read as 0. The write value should be 0.
R/W