15. Buses
15.2.6
Parallel Operation
Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For
example, if the CPU is fetching an instruction from on-chip ROM and an operand from on-chip RAM, the DMACA is
able to handle transfer between a peripheral bus and the external bus at the same time.
An example of parallel operations is shown in
Figure 15.5. In this example, the CPU is able to employ the instruction
and operand buses for simultaneous access to on-chip ROM and on-chip RAM, respectively. Furthermore, the DMACA
simultaneously employs internal main bus 2 for access to a peripheral bus or the external bus during access to on-chip
RAM and ROM by the CPU.
Figure 15.5
Example of Parallel Operations
15.2.7
Bus Settings
(1) Set the mode of the external bus in the CSn mode register (CSnMOD), CSn wait-control register 1 (CSnWCR1),
CSn wait-control register 2 (CSnWCR2), CSn control register (CSnCR), CSn recovery-cycle setting register
(CSnREC), CS recovery cycle insertion enable register (CSRECEN), bus-error monitoring-enable register
(BEREN), and bus-priority control register (BUSPRI).
(2) Make settings for pins in the CS output enable register (PFCSE), address output enable register 0 (PFAOE0),
address output enable register 1 (PFAOE1), external-bus control register 0 (PFBCR0), and external-bus control
register 1 (PFBCR1).
(3) Set up pins to be used as input port pins.
(4) Set the external-bus enable bit (EXBE) in the system control register 0 (SYSCR0) to 1 (enabling the external bus).
15.2.8
Restrictions
(1) Prohibition of Access that Spans Areas of Address Space
Single access that spans two areas of the address space is prohibited, and operation of such an access is not guaranteed.
Setting must be made so that two areas are not accessed at the same time by a single word or longword access.
(2) Restrictions in relation to RMPA and string-manipulation instructions
(a)
Although the external space has a per-area ending-switching facility (only for data), the allocation of data to be
handled by RMPA or string-manipulation instructions to an area where the endian differs from that of the chip is
prohibited, and operation is not guaranteed if this restriction is not observed. If data to be handled by RMPA or
string-manipulation instructions are allocated to the external space, they must be allocated to areas where the
endian setting is the same as that for the chip.
(b) The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited,
and operation is not guaranteed if this restriction is not observed.
CPU operand
RAM
ROM
CPU instruction
fetching
DMACA
Peripheral bus
External bus
On-chip ROM access
On-chip RAM access
Peripheral bus access
External bus access
ROM
RAM