11. Low Power Consumption
Figure 11.1
Mode Transitions
All-module clock stop
mode
Sleep mode
All interrupts
Low power consumption mode
(Program stopped state)
SBYCR.SSBY = 0
MSTPCRA.ACSE = 1
MSTPCRA = FFFF FF[C-F]Fh
MSTPCRB = FFFF FFFFh
Upper 16 bits in MSTPCRC = FFFFh
Interrupt*
4
Interrupt*3
WAIT instruction*1
Interrupt*2
WAIT instruction*1
WAIT
instruction*1
RES# pin = High*5
Note 1. If an interrupt that becomes a canceling source is accepted while making a transition to the program stop state after the WAIT instruction
has been executed, the transition to the program stop state is canceled and the interrupt exception handling is executed.
Note 2. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the 8-bit timer, RTC alarm,
RTC interval, IWDT, voltage-monitoring 1, voltage-monitoring 2, and oscillator-stopped detection interrupts). However, an 8-bit timer
interrupt is only effective when the value of the corresponding module-stop setting bit (MSTPA4 or MSTPA5, respectively) in module-stop
control register A (MSTPCRA) for 8-bit timer 0 and 1 (unit 0) or 2 and 3 (unit 1) is 0.
Note 3. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the RTC alarm, RTC interval,
IWDT, voltage-monitoring 1, and voltage-monitoring 2 interrupts).
Note 4. “Interrupts” here indicates a certain external pin interrupt source pin (the NMI, IRQ0-DS to IRQ7-DS, SCL-DS, or SDA-DS) or any of
peripheral interrupts (the RTC alarm, RTC interval, voltage-monitoring 1, and voltage-monitoring 2 interrupts).
Note 5. The LOCO is the source of the operating clock following a transition from the reset state to normal operating mode.
Note 6. Makes a transition from sleep mode, all-module clock stop mode, or software standby mode to normal operating mode by an interrupt. In
the case of recovery from sleep mode, the clock source for subsequent use is selectable.
For details, see section 11.2.6, Sleep Mode Return Clock Source Switching Register (RSTCKCR). For software standby mode, the clock
source after returning is the same as that before returning.
Note 7. When an interrupt request as indicated in Note 4 above is generated, an internal reset (deep software standby reset) is generated over a
fixed period. Release from deep software standby mode accompanies release from the internal reset state. When deep software standby
mode is canceled, a transition to normal operating mode is made, and reset exception handling starts with the LOCO as the source of the
operating clock.
When a pin reset, power-on reset, voltage-monitoring 0 reset, watchdog timer reset, or independent watchdog timer reset is generated in any state,
a transition to the reset state is made.
SBYCR.SSBY = 0
Internal reset state
Software standby
mode
Deep software
standby mode
Reset state
*7
SBYCR.SSBY=1
Normal operation mode
(Program execution state)*6
DPSBYCR.DPSBY = 0
DPSBYCR.DPSBY = 1