30. Serial Peripheral Interface (RSPI)
30.
Serial Peripheral Interface (RSPI)
30.1
Overview
The
RX210 Group includes one independent channels of Serial Peripheral Interface (RSPI).
The RSPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors
and peripheral devices.
Also, m as used with the RSPI command registers (SPCMDm) indicates 0 to 7.
Table 30.1
Specifications of RSPI
Item
Description
Number of channels
One channel
RSPI transfer functions
Use of MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (RSPI
clock) signals allows serial communications through SPI operation (four-wire method) or clock
synchronous operation (three-wire method).
Transmit-only operation is available.
Capable of serial communications in master/slave mode
Switching of the polarity of the serial transfer clock
Switching of the phase of the serial transfer clock
Data format
MSB-first/LSB-first selectable
Transfer bit length is selectable as 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits.
128-bit transmit/receive buffers
Up to four frames can be transferred in one round of transmission/reception (each frame consisting of
up to 32 bits).
Buffer configuration
Double buffer configuration for the transmit/receive buffers
Error detection
Mode fault error detection
Overrun error detection
Parity error detection
SSL control function
Four SSL signals (SSLA0 to SSLA3) for each channel
In single-master mode, SSLA0 to SSLA3 signals are output.
In multi-master mode:
SSLA0 signal for input, and SSLA1 to SSLA3 signals for either output or unused.
In slave mode:
SSLA0 signal for input, and SSLA1 to SSLA3 signals for unused.
Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable delay from RSPCK stop to SSL output negation (SSL negation delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Controllable wait for next-access SSL output assertion (next-access delay)
Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units)
Function for changing SSL polarity
Control in master transfer
A transfer of up to eight commands can be executed sequentially in looped execution.
For each command, the following can be set:
SSL signal value, bit rate, RSPCK polarity/phase, transfer data length, MSB/LSB-first, burst, RSPCK
delay, SSL negation delay, and next-access delay
A transfer can be initiated by writing to the transmit buffer.
MOSI signal value specifiable in SSL negation
Interrupt sources
Maskable interrupt sources
RSPI receive interrupt (receive buffer full)
RSPI transmit interrupt (transmit buffer empty)
RSPI error interrupt (mode fault, overrun, parity error)
RSPI idle interrupt (RSPI idle)
Event linking
The following five types of events can be output to the event link controller.
Reception-buffer full signal
Transmission-buffer empty signal
Mode fault, overrun, or parity error signal
RSPI idle signal
Transmission-completed signal