21. Multi-Function Timer Pulse Unit 2 (MTU2A)
(1) Example of Complementary PWM Mode Setting Procedure
Figure 21.38 shows an example of the complementary PWM mode setting procedure.
Figure 21.38
Example of Complementary PWM Mode Setting Procedure
[1]
Clear bits CST3 and CST4 in the timer start register (TSTR) to 0 to stop
timer counter (TCNT) operation. Specify complementary PWM mode while
MTU3.TCNT and MTU4.TCNT are stopped.
[2]
Set the same counter clock and clock edge for MTU3 and MTU4 with bits
TPSC[2:0] and bits CKEG[1:0] in the timer control register (TCR). Use bits
CCLR[2:0] to set synchronous clearing only when restarting by
synchronous clearing with another channel during complementary PWM
mode operation.
[3]
When performing brushless DC motor control, set bit BDC in the timer gate
control register (TGCR) and set the feedback signal input source and
output chopping or gate signal direct output.
[4]
Set the dead time in MTU3.TCNT. Set MTU4.TCNT to 0000h.
[5]
Set only when restarting by synchronous clearing with another channel
during complementary PWM mode operation. In this case, synchronize the
channel generating the synchronous clear with MTU3 and MTU4 using the
timer synchronous register (TSYR).
[6]
Set the output PWM duty cycles in the duty registers (MTU3.TGRB,
MTU4.TGRA, and MTU4.TGRB) and buffer registers (MTU3.TGRD,
MTU4.TGRC, and MTU4.TGRD). Set the same value in the buffer
registers and the duty registers.
[7]
This setting is necessary only when no dead time should be generated .
Make appropriate settings in the timer dead time enable register (TDER)
so that no dead time is generated.
[8]
Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in
the carrier cycle data register (TCDR) and carrier cycle buffer register
(TCBR), and 1/2 the carrier cycle plus the dead time in MTU3.TGRA and
MTU3.TGRC. When no dead time generation is selected, set 1 in TDDR
and 1/2 the carrier cycle + 1 in MTU3.TGRA and MTU3.TGRC.
[9]
Enable or disable toggle output synchronized with the PWM cycle using bit
PSYE in the timer output control register 1 (TOCR1), and set the PWM
output level with bits OLSP and OLSN.
When specifying the PWM output level by using TOLBR as a buffer for
MTU2.TOCR, see Figure 21.3, Example of PWM Output Level Setting
Procedure in Buffer Operation.
[10] Select complementary PWM mode in the timer mode register
(MTU3.TMDR). Set the BFA bit of TGRA and TGRC to 1 for buffer
operation of TGRA and TGRC, and the BFB bit to 1 for buffer operation of
TGRB and TGRD, if necessary. Set nothing in MTU4.TMDR.
[11] Set enabling/disabling of PWM waveform output pin output in the timer
output master enable register (TOER).
[12] Set the I/O port and MPC.
[13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count
operation.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[11]
[10]
[12]
[13]
<Complementary PWM mode>
Start count operation
Pin setting
Enable waveform output
Complementary PWM mode
setting
Enable PWM cyclic output,
set PWM output level
Dead time, carrier cycle
setting
Enable/disable dead time
generation
TGR setting
Inter-channel synchronization
setting
TCNT setting
Brushless DC motor control
setting
Counter clock, counter clear
source selection
Stop count operation
Complementary PWM mode