REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
REVISION HISTORY
Rev.
Date
Description
Page
Summary
0.50
Mar. 17, 2011
—
First edition, issued
0.51
Apr.15, 2011
All
DMACA activation source select register
DMACA activation request select register
3. Operating Modes
95
Table 3.3 Endian Setting Method, changed
7. Option-Setting Memory
141
Figure 7.1 Option-Setting Memory Area, changed
9. Clock Generation Circuit
198
9.9 Pin Settings When an External Clock is Connected: Description changed
11. Low Power Consumption
221
11.2.2 Module Stop Control Register A (MSTPCRA): ACSE Bit (All-Module Clock Stop Mode
Enable), changed
226
Table 11.4 Relationship between Operating Power Control Mode, Operating Range, and Power
Consumption, changed
231
11.2.9 Deep Standby Control Register (DPSBYCR): Description changed
239
11.2.16 Flash HOCO Sofware Standby Control Register (FHSSBYCR): Description changed
245
11.6.2.1 Transition to All-Module Clock Stop Mode: Description changed
18. Event Link Controller (ELC)
458
18.2.2 Event Link Setting Register n (ELSRn) (n = 1 to 4, 7, 10, 12, 15, 16 and 18 to 29):
Description changed
20. Multifunction Pin Controller (MPC)
520
Table 20.9 Register Settings for Input/Output Pin Function in 64-Pin LQFP, changed
21. Multi-Function Timer Pulse Unit 2 (MTU2A)
558
21.2.3 Timer I/O Control Register (TIOR): Description changed
632
Figure 21.35 Procedure for Selecting Reset-Synchronized PWM Mode, changed
23. 23. 8-Bit Timer (TMR)
778
23.8 Link Operation by ELC: Description changed
25. Realtime Clock (RTCA)
All in this
section
Pin name changed: XRTCIN
XCIN, XRTCOUT XCOUT, RTCTC0 RTCIC0,
RTCTC1
RTCIC1, RTCTC2 RTCIC2
26. Watchdog Timer (WDT)
836
Table 26.2 WDT Registers: Address in Option function select register 0, changed
27. Independent Watchdog Timer (IWDT)
All in this
section
Symbol name changed: OCOCLK
IWDTCLK
855
Table 27.2 IWDT Registers: Address in Option function select register 0, changed
30. Serial Peripheral Interface (RSPI)
1095
SPEIE Bit (RSPI Error Interrupt Enable): Description changed
1165
30.5 Usage Note: Description changed
32. 12-Bit A/D Converter (S12AD)
1178
32.2.1 A/D Data Registers y (ADDRy) (y = 0 to 15): Description changed
1186
ADCS [1:0] Bit (Scan Mode Select): Description changed
39. ROM (Flash Memory for Code Storage)
1309
Table 39.8 FCU Command Formats, changed
40. E2 Data Flash Memory (Flash Memory for Data Storage)
1368
40.2.6 Flash P/E Mode Entry Register (FENTRYR): Description changed
1369
40.2.7 E2 Data Flash Blank Check Control Register (DFLBCCNT): Description changed
1374
40.6.1.3 E2 Data Flash P/E Modes: (1), description changed
1375
Table 40.5 FCU Commands for Use with E2 Data Flash Memory, changed
1379
(4) Blank Checking: Description changed
0.90
Aug. 09, 2011 1. Overview
41
Table 1.1 Outline of Specifications: Power supply voltage/ Operating frequency, changed
54, 58, 61,
63
Table 1.5 to Table 1.8 List of Pins and Pin Functions (Pin name: LVCMP2
CMPA2), changed
2. CPU
REVISION HISTORY