32. 12-Bit A/D Converter (S12AD)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
32.3.2.7
A/D Conversion in Double Trigger Mode
In single-cycle scan mode with double trigger mode, single-cycle scan operation started by the MTU or ELC trigger is
performed twice as below.
Self-diagnosis should be deselected, and the temperature sensor output A/D conversion select bit (TSS) and internal
reference voltage A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection).
Duplication of A/D conversion data is enabled by setting the channel numbers to be duplicated to the DBLANS[4:0] bits
in ADCSR and setting the DBLE bit in ADCSR to 1. When the DBLE bit in ADCSR is set to 1, channel selection using
the ADANSA register is invalid. In double trigger mode, MTU or ELC triggers should be selected using the TRSA[3:0]
bits in ADSTRGR; the EXTRG bit and TRGE bit in ADCSR should be set to 0 and 1, respectively. Software trigger
should not be used.
(1) When the ADST bit in ADCSR is set to 1 (A/D conversion start) by the MTU or ELC trigger input, A/D conversion
is started on the single channel selected by the DBLANS[4:0] bits in ADCSR.
(2) When A/D conversion is completed, the A/D conversion result is stored into the corresponding A/D data register
(ADDRy).
(3) The ADST bit is automatically cleared to 0 and the 12-bit A/D converter enters a wait state. Here, an S12ADI0
interrupt request is not generated irrespective of the ADIE (S12ADI0 interrupt upon scanning completion enabled)
bit setting in ADCSR.
(4) When the ADST bit in ADCSR is set to 1 (A/D conversion start) by the second trigger input, A/D conversion is
started on the single channel selected by the DBLANS[4:0] bits in ADCSR.
(5) When A/D conversion is completed, the A/D conversion result is stored into the A/D data duplication register
(ADDBLDR), which is exclusively used in double trigger mode.
(6) If the ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled), an S12ADI0 interrupt
request is generated.
(7) The ADST bit remains 1 (A/D conversion start) during A/D conversion, and is automatically cleared to 0 when A/D
conversion is completed. Then the 12-bit A/D converter enters a wait state.
Figure 32.9
Example of Operation in Single-Cycle Scan Mode (Double Trigger Mode Selected; AN003
Duplicated)
Waiting for conversion
ADST
A/D conversion
started
Channel 3 (AN003)
Waiting for
conversion
ADDR3
ADDBLDR
S12ADI0
A/D conversion 1
Set
(1)
Stored
A/D conversion result 1
A/D conversion result 2
A/D conversion time
A/D conversion
performed once
(2)
(6)
Waiting for conversion
Interrupt generated
(3)
Set
A/D conversion 2
A/D conversion time
Stored
(6)
(5)
(7)
(4)
Trigger (TRG4ABN)
A/D conversion
performed once
Note: In the figure, AN003 is set to be duplicated and the TRG4ABN trigger is selected.