22. Port Output Enable 2 (POE2)
22.3.3
High-Impedance Control Using Registers
The high-impedance of the MTU2A complementary PWM output and MTU0 pins can be directly controlled using the
software port output enable register (SPOER).
Setting the CH34HIZ bit in SPOER to 1 places the MTU2A complementary PWM output pins (MTU3 and MTU4)
specified by the port output enable control register 2 (POECR2) in the high-impedance.
Setting the CH0HIZ bit in SPOER to 1 places the MTU0 output pins specified by the port output enable control register 1
(POECR1) in the high-impedance.
22.3.4
High-Impedance Control on Detection of Stopped Oscillation
When the oscillation-stop detection circuit in the clock pulse generator detects stopped oscillation, pins for
complementary PWM output by POECR2 and the MTU0 output pins specified by POECR1 are placed in the high-
impedance.
22.3.5
When Event Signals Received from the ELC Control the High-Impedance
Pins for complementary PWM output from the MTU2A and output pins for MTU0 can be placed in high-impedance by
an event signal from the event link controller (ELC).
When the ELC is used to control high-impedance of pins for complementary PWM output from the MTU2A and output
pins for MTU0, the each bits of the POECR1 and POECR2 registers should be set to 1. Then ,when an event signal is
input, the corresponding bit of the SPOER register (CH0HIZ or CH34HIZ) is set to 1 and pins for complementary PWM
output from the MTU2A or output pins for MTU0 becomes the high impedance.
22.3.6
Release from the high-impedance
Pins for complementary PWM output from MTU2A and pins for MTU0 which have been placed in the high-impedance
due to input-level detection can be released from that state by either returning them to their initial state with a reset or
clearing all of the POE3F to POE0F flags in ICSR1 and the POE8F flag in ICSR2. Note, however, that when low-level
sampling is selected by the POE3M[1:0] to POE0M[1:0] bits in ICSR1 and the POE8M[1:0] bits in ICSR2, if a high
level is being input to the corresponding pin from among POE0# to POE3# and POE#8 but has not yet been sampled,
writing 0 to the flag is ignored (the flag is not cleared).
MTU2A complementary PWM output pins which have been placed in the high-impedance due to output-level
comparison can be released from that state by either returning them to their initial state with a reset or clearing the OSF1
flag in OCSR1. Note, however, that if the inactive level is not yet being output from the MTU2A complementary PWM
output pins, writing 0 to the flag is ignored (the flag is not cleared). Inactive-level outputs can be obtained by setting the
MTU2A registers.
For MTU2A complementary PWM output pins and pins for MTU0 that have been placed in the high-impedance because
oscillation by the clock generation circuit has stopped, clearing the OSTSTF or OSTSTE bit in ICSR3 releases the pins
from the high-impedance.
For MTU2A complementary PWM output pins and pins for MTU0 that have been placed in the high-impedance by the
SPOER.CH34HIZ or SPOER.CH0HIZ bit, clearing the corresponding bits (SPOER, CH34HIZ and CHOHIZ) releases
the pins from the high-impedance.