29. I2C Bus Interface (RIIC)
29.11.2
Extra SCL Clock Cycle Output Function
In master mode, the RIIC module has a facility for the output of extra SCL (clock) cycles to release the SDA0 line of the
slave device from being held at the low level due to the master being out of synchronization with the slave device.
This function is mainly used in master mode to release the SDA0 line of the slave device from the state of being fixed to
the low level by including extra cycles of SCL0 output from the RIIC with single cycles of the SCL (clock) signal as the
unit in the case of a bus error where the RIIC cannot issue a stop condition because the slave device is holding the SDA0
line at the low level. Do not use this facility in normal situations. Using it when communications are proceeding correctly
will lead to malfunctions.
When the CLO bit in ICCR1 is set to 1 in master mode, a single cycle of the SCL clock at the frequency corresponding to
the transfer rate settings (settings of the CKS[2:0] bits in ICMR1, and of the ICBRH and ICBRL registers) is output as an
extra clock cycle. After output of this single cycle of the SCL clock, the CLO bit is automatically cleared to 0. Therefore,
further extra clock cycles can be output consecutively by the software program writing 1 to the CLO bit after having read
CLO = 0.
When the RIIC module is in master mode and the slave device is holding the SDA0 line at the low level because
synchronization with the slave device has been lost due to the effects of noise, etc., the output of a stop condition is not
possible. The facility for output of an extra cycle of the SCL (clock) signal can be used to output extra cycles of SCL one
by one to make the slave device release the SDA0 line from being held at the low level, thus recovering the bus from an
unusable state. Release of the SDA0 line by the slave device can be monitored by reading the SDAI bit in ICCR1. After
confirming release of the SDA0 line by the slave device, complete communications by reissuing the stop condition.
Use this facility with the MALE bit (master arbitration-lost detection disabled) in ICFER cleared to 0. If the MALE bit is
set to 1 (master arbitration-lost detection enabled), arbitration is lost when the value of the SDAO bit in ICCR1does not
match the state of the SDA0 line, so take care on this point.
[Output conditions for using the CLO bit in ICCR1]
When the bus is free (BBSY flag in ICCR2 = 0) or in master mode (MST bit = 1 and BBSY flag = 1 in ICCR2)
When the communication device does not hold the SCL0 line low
Figure 29.39 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
Figure 29.39
Extra SCL Clock Cycle Output Function (CLO Bit)
Write 1 to CLO
Accept CLO output
Write 1 to CLO
Data“1”
MSB or Next Data
ICBRH
ICBRL
ICBRH
ACK or Data“0”
ICBRL
ICBRH
9
Extra clock cycle
output
Extra clock cycle
output
TRS
MST
BBSY
IIC
SCL0
SDA0
CLO
SDA0 line is held low due to irregular bits
Release SDA0 line