10. Clock Frequency Accuracy Measurement Circuit (CAC)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
10.3
Operation
10.3.1
Measuring Clock Frequency Based on CACREF Pin Input
Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit based on the CACREF
pin input.
The clock frequency accuracy measurement circuit operates as shown below when measuring the clock frequency.
(1) Writing 1 to the CFME bit in CACR0 while the RPS bit in CACR2 is 0 and the CACREFE bit in CACR1 is 1
enables clock-frequency measurement based on the CACREF pin input.
(2) After 1 is written to the CFME bit, the timer starts up-counting when the valid edge selected by the EDGES[1:0]
bits in CACR1 is input from the CACREF pin.
(3) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. If both CACNTBR
CAULVR and CACNTBR CALLVR are satisfied, only the
MENDF flag in CASTR is set to 1 because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a
measurement end interrupt will occur.
(4) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(5) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(6) While the CFME bit in CACR0 is 1, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops up-counting.
Figure 10.2
Operating Example of Clock Frequency Accuracy Measurement Circuit Based on CACREF Pin
Input
0000h
CAULVR
CALLVR
Counter value
FFFFh
Time
7FFFh
3FFFh
BFFFh
0000h
MENDF flag in CASTR
(measurement end flag)
(1)
(2)
(3)
(4)
(5)
(6)
The above figure applies under the following conditions:
In CACR1: CACREFE bit = 1, EDGES0 bit = 0, and EDGES1 bit = 0
CAULVR = AAAAh, CALLVR = 5555h
“1”
“0”
FERRF flag in CASTR
(frequency error flag)
“1”
“0”
CACNTBR
CFME bit in CACR0
“1”
“0”
CACREF pin
“1”
“0”
1 is written to
CFME bit.
1 is written to MENDFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
1 is written to FERRFCL
bit in CAICR.
1 is written to MENDFCL
bit in CAICR.
1 is written to FERRFCL
bit in CAICR.
0 is written to
CFME bit.
Counter is
cleared by writing
0 to CFME bit.
After 1 is written to CFME bit, counting
starts at the first valid edge.