9. Clock Generation Circuit
9.5
Oscillation Stop Detection Function
9.5.1
Oscillation Stop Detection and Operation after Detection
The oscillation stop detection function is used to detect the main clock oscillator stop and to supply low-speed clock
pulses from the low-speed clock oscillator as the system clock source instead of the main clock or PLL clock.
An oscillation stop detection interrupt request can be generated when an oscillation stop is detected. In addition, the
MTU2 output can be forcedly driven to the high-impedance on the detection. For details, see
section 21, Multi-In
RX210 Group, the main clock oscillation stop is detected when the input clock remains to be 0 or 1 for a certain
When an oscillation stop is detected, the main clock or PLL clock selected by the clock source select bits
(SCKCR3.CKSEL[2:0]) is switched to the low-speed clock by the corresponding selectors in the former stage.
Therefore, if an oscillation stop is detected with the main clock or PLL clock selected as the system clock source, the
system clock source is switched to the low-speed clock without a change of CKSEL[2:0].
Switching between the main clock and low-speed clock or between the PLL clock and low-speed clock is controlled by
the oscillation stop detection flag (OSTDSR.OSTDF). The clock source is switched to the low-speed clock when the
OSTDF bit is 1, and is switched to the main clock or PLL clock again when the OSTDF bit is cleared to 0. At this time,
if the main clock or PLL clock is selected with the CKSEL[2:0] bits, the OSTDF bit cannot be cleared to 0. To switch the
clock source to the main clock or PLL clock again after the oscillation stop detection, set the CKSEL[2:0] bits to a clock
source other than the main clock or PLL clock and clear the OSTDF bit to 0. After that, check that the OSTDF is not 1,
and then set the CKSEL[2:0] bits to the main clock or PLl clock after the specified oscillation settling time has elapsed.
After a reset is released, the main clock oscillator is stopped and the oscillation stop detection function is disabled. To
enable the oscillation stop detection function, activate the main clock oscillator and write 1 to the oscillation stop
detection function enable bit (OSTDCR.OSTDE) after a specified oscillation settling time has elapsed.
The oscillation stop detection function is provided against the main clock stop by an external cause. Therefore, the
oscillation stop detection function should be disabled before the main clock oscillator is stopped by the software or a
transition is made to software standby mode or deep software standby mode.
The clocks that are switched to the low-speed clock by the oscillation stop detection are: the main clock, PLL clock, and
CAC main clock (CACMCLK), which are provided as the system clock sources.
The system clock (ICLK) frequency during the low-speed clock operation is specified by the LOCO oscillation
frequency and the division ratio set by the system clock select bits (SCKCR.ICK[3:0])