15. Buses
15.5.4
Insertion of Recovery Cycles
Recovery cycles can be inserted between consecutive rounds of external bus access by setting the recovery cycle
insertion enable bit in CSRECEN to 1.
The number of recovery cycles to be inserted after read cycles and write cycles can be separately set for each area using
CSnREC. When the preceding bus cycle is a write access, the number of write recovery cycles should be set with the
WRCV[3:0] bits for the area. When the preceding bus cycle is a read access, the number of read recovery cycles should
be set with the RRCV[3:0] bits for the area. For example, when CS1 read access occurs after CS0 read access, the
number of recovery cycles to be inserted between them is set by the RRCV[3:0] bits in CS0REC.
Recovery cycles can be inserted on any of the following eight conditions. The recovery cycle insertion can be enabled or
disabled with the RCVENj (j = 0 to 7) in CSRECEN when the preceding bus access is a separate bus access, and with
RCVENMj (j = 0 to 7) when the preceding bus access is an address/data multiplexed bus access.
After a read access to the external bus, a read access is made to the external bus in the same area.
After a read access to the external bus, a read access is made to the external bus in a different area.
After a read access to the external bus, a write access is made to the external bus in the same area.
After a read access to the external bus, a write access is made to the external bus in a different area.
After a write access to the external bus, a read access is made to the external bus in the same area.
After a write access to the external bus, a read access is made to the external bus in a different area.
After a write access to the external bus, a write access is made to the external bus in the same area.
After a write access to the external bus, a write access is made to the external bus in a different area.
The recovery cycle starts at the end of the preceding bus cycle, i.e. when the CSn# signal (n = 0 to 7) is negated. A high-
level period of the CSn# signal is inserted for the specified recovery cycle period starting from this point.
The CSn# signal for the next round of bus access is asserted immediately after the end of recovery cycles in the fastest
case. Even if the next request for access to an external address space is generated during the recovery period, the next
round of access over the external bus will start immediately after the end of recovery cycles.
When two or more external bus access cycles are required for a single transfer request from a bus master and the
recovery cycle insertion condition is satisfied, recovery cycles are also inserted between these bus access cycles.
However, when page read access is enabled (CSnMOD.PRENB = 1) or page write access is enabled (CSnMOD.PWENB
= 1), recovery cycles are not inserted except after the last bus access cycle of the transfer even if the recovery cycle
insertion condition is satisfied (
Figure 15.34). Similarly, during normal accesses with page access enabled, recovery
cycles are not inserted between bus access cycles but inserted only after the last bus access cycle of the transfer.
Similarly, during normal accesses with page access enabled, with the separate bus interface, recovery cycles are not
inserted between bus access cycles but inserted only after the last bus access cycle of the transfer. With the address/data
multiplexed I/O interface, when the recovery cycle insertion condition is satisfied, recovery cycles are inserted between
bus access cycles regardless of the page access enable setting.