32. 12-Bit A/D Converter (S12AD)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
32.3.3.2
Basic Operation (Channel-Dedicated Sample-and-Hold Circuits Used)
When the channel-dedicated sample-and-hold circuit is used, sample-and-hold operation is first performed, and then A/D
conversion is repeated on the analog input of all the selected channels as below. The channels whose channel-dedicated
sample-and-hold circuit is to be used can be selected by the SHANS[2:0] bits in ADSHCR.
In continuous scanning mode, temperature sensor output A/D conversion select bit (TSS) and internal reference voltage
A/D conversion select bit (OCS) in ADEXICR should both be set to 0 (non-selection).
(1) Analog input sampling of all the channels whose channel-dedicated sample-and-hold circuit is to be used is started
when the ADST bit in ADCSR is set to 1 (A/D conversion start) by software or synchronous trigger (MTU or ELC)
input.
(2) After sample-and-hold operation, A/D conversion is performed for ANn channels selected by the ADANSA
register, starting from the channel with the smallest number n.
(3) Each time A/D conversion of a single channel is completed, the A/D conversion result is stored into the
corresponding A/D data register (ADDRy).
(4) When A/D conversion of all the selected channels is completed, an S12ADI0 interrupt request is generated if the
ADIE bit in ADCSR is 1 (S12ADI0 interrupt upon scanning completion enabled). At the same time, analog input
sampling is started for all the channels whose channel-dedicated sample-and-hold circuit is to be used.
(5) The ADST bit is not automatically cleared to 0 and steps 2 to 4 are repeated as long as the bit remains 1. When the
ADST bit is set to 0 (A/D conversion stop), A/D conversion stops and the 12-bit A/D converter enters a wait state.
(6) When the ADST bit is later set to 1 (A/D conversion start), analog input sampling is started again for all the
channels whose channel-dedicated sample-and-hold circuit is to be used.
Figure 32.11
Example of Operation in Continuous Scan Mode (Channel-Dedicated Sample-and-Hold Circuits
Used)
ADST
A/D conversion
started
Channel 0 (AN000) Waiting for conversion
Channel 1 (AN001) Waiting for conversion
ADDR0
ADDR1
S12ADI0
Sampling
Set
(1)
(3)
Stored
A/D conversion 1
Holding
Cleared
(5)
A/D conversion result 1
A/D conversion result 2
A/D conversion result 3
A/D conversion
time
Sampling-and-holding and scanning performed repeatedly
(3)
(4)
Set
(6)
Note: Data for A/D conversion 4 is ignored.
Interrupt generated
Stored
Sampling
Holding
A/D conversion 2
Sample-and-hold time
Sampling
Holding A/D conversion 3
Sampling
Holding
Waiting for conversion
(2)
A/Dconversion4*
1
Waiting for conversion
Waiting for
conversion
Sampling
(2)
(3)
Stored