11. Low Power Consumption
“Operating possible” means that operating or stopped can be controlled by the control register setting.
“Stopped (Retained)” means that internal register values are retained and internal operations are suspended.
“Stopped (Undefined)” means that internal register values are undefined and power is not supplied to the internal circuit.
Note 1. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the 8-bit timer, RTC
alarm, RTC interval, IWDT, USB suspend/resume, voltage-monitoring 1, voltage-monitoring 2, and oscillator-stopped detection
interrupts).
Note 2. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the RTC alarm,
RTC interval, IWDT, voltage-monitoring 1, and voltage-monitoring 2 interrupts).
Note 3. “Interrupts” here indicates a certain external pin interrupt source pin (the NMI, IRQ0-DS to IRQ7-DS, SCL-DS, SDA-DS) or any
of peripheral interrupts (the RTC alarm, RTC interval, voltage-monitoring 1, and voltage-monitoring 2 interrupts). However, these
interrupts are enabled only when the corresponding bit in the deep standby interrupt enable registers i (DPSIERi) (i = 0, 2) is set
to 1. A pin with a name having the suffix “-DS” can be used to initiate release from deep software standby mode.
Note 4. This does not include release initiated by a reset on the RES# pin, power-on reset, voltage-monitoring reset, or independent
watchdog-timer reset. The transition is to the reset state when release is initiated by one of these reset sources.
Note 5. Operation or stopping can be selected by the main clock oscillator forcible oscillation control bit (MOFXIN) in the main clock
oscillator forcible oscillation control register (MOFCR).
Note 6. Operation or stopping is selected by the sub-clock control bit (RTCEN) in the RTC control register 3 (RCR3).
Note 7. Operation or stopping is selected by the setting of the IWDT sleep mode counter stop control bit (IWDTSLCSTP) in the option
function select register 0 (OFS0) in IWDT auto start mode. If the OFS0.IWDTSLCSTP bit is 0 (disabling stopping of the counter
when a transition to low power consumption mode is made), the transition is to software standby mode rather than deep
software standby mode. In any mode other than IWDT auto start mode, operation or stopping is selected by the setting of the
sleep mode counter stop control bit (SLCSTP) in the IWDT counter stop control register (IWDTCSTPR). If the
IWDTCSTPR.SLCSTP bit is 0 (disabling stopping of the counter when a transition to low power consumption mode is made), the
transition is to software standby mode rather than deep software standby mode.
Note 8. Stopping or operation is controlled by the module-stop setting bits (MSTPA4 and MSTPA5, respectively) in module-stop control
register A (MSTPCRA) for 8-bit timers 0 and 1 (unit 0) and 2 and 3 (unit 1).
Note 9. In the case of a transition to software standby mode when the setting of the software cut bit in the flash HOCO software standby
control register (FHSSBYCR.SOFTCUT2) is 1 or a transition to deep software standby mode when the setting of the deep cut bit
in the deep standby control register (DPSBYCR.DEEPCUT1) is 1, the voltage-monitoring circuits are stopped and the low power
consumption function of the power-on reset circuit is enabled.
Note 10. If the voltage-monitoring 1 circuit mode selection bit in the voltage-monitoring 1 circuit control register 0 (LVD1CR0.LVD1RI) or
Table 11.2
Entering and Exiting Low Power Consumption Modes and Operating States in Each Mode
Entering and Exiting Low Power
Consumption Modes and Operating
States
Sleep Mode
All-Module Clock Stop
Mode
Software Standby Mode
Deep Software Standby
Mode
Transition condition
Control register +
instruction
Control register +
instruction
Control register +
instruction
Control register +
instruction
Canceling method other than reset
Interrupt
State after cancellation
*4Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Program execution state
(interrupt processing)
Program execution state
(reset processing)
Main clock oscillator
Operating possible
Sub-clock oscillator
Operating possible
High-speed clock oscillator
Operating possible
Stopped
Low-speed clock oscillator
Operating possible
Stopped
Dedicated low-speed clock oscillator for the
IWDT
PLL
Operating possible
Stopped
CPU
Stopped (Retained)
Stopped (Undefined)
On-chip RAM0
(0000 0000h to 0000 FFFFh)
Operating possible
(Retained)
Stopped (Retained)
Stopped
(Undefined)
Flash memory
Operating
Stopped (Retained)
Watchdog timer (WDT)
Stopped (Retained)
Stopped (Undefined)
Independent watchdog timer (IWDT)
Realtime clock (RTCA)
Operating possible
8-bit timer (unit 0, unit 1) (TMR)
Operating possible
Stopped (Retained)
Stopped (Undefined)
Voltage detection circuit (LVD)
Operating possible
Operating possible
Power-on reset circuit
Operating
Peripheral modules
Operating possible
Stopped (Retained)
Stopped (Undefined)
I/O ports
Operating