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32. 12-Bit A/D Converter (S12AD)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
32.3.6
Usage Example of Automatic Register Clearing Function
Setting the ACE bit in ADCER to 1 automatically clears the A/D data registers (ADDRy, ADRD, ADTSDR, ADOCDR,
and ADDBLDR) to 0000h when the A/D data registers are read by the CPU, DTC, or DMACA.
This function enables detection of update failures of the A/D data registers. The following describes the examples in
which the function to automatically clear the ADDRy register is enabled and disabled.
In a case where the ACE bit in ADCER is 0 (automatic clearing is disabled), if the A/D conversion result (0222h) is not
written to the ADDRy register for some reason, the old data (0111h) will be the ADDRy value. Furthermore, if this
ADDRy value is written to a general register using an A/D scan end interrupt, the old data (0111h) can be saved in the
general register. When checking whether there is an update failure, it is necessary to frequently save the old data in the
RAM or a general register.
In a case where the ACE bit in ADCER is 1 (automatic clearing is enabled), when ADDRy = 0111h is read by the CPU,
DTC, or DMACA, ADDRy is automatically cleared to 0000h. After that, if the A/D conversion result 0222h cannot be
transferred to ADDRy for some reason, the cleared data (0000h) remains as the ADDRy value. If this ADDRy value is
read into a general register using an A/D scan end interrupt at this point, 0000h will be saved in the general register.
Occurrence of an ADDRy update failure can be determined by simply checking that the read data value is 0000h.
32.3.7
A/D-Converted Value Addition Function
The same channel is A/D converted two to four consecutive times and the sum of the converted values is stored in the
data register. The use of the average of these results can improve the accuracy of A/D conversion, depending on the types
of noise components that are present. This function, however, cannot always guarantee an improvement in A/D
conversion accuracy.
A/D converted value addition function can be used for channel-selected analog input A/D conversion and internal
reference voltage A/D conversion.
32.3.8
Disconnection Detection Assist Function
The charge of the sampling capacitors can be fixed to the specified level (VREFH0 or VREFL0) before A/D conversion.
This function enables detection of disconnection of the wires connected to the analog inputs.
the example of disconnection detection at the VREFH0 (precharge is selected) and
Figure 32.20 shows the example of
disconnection detection at the VREFL0 side (discharge is selected).
Figure 32.18
A/D Conversion with Disconnection Detection Assist Function Used
ADST
Fixed to 30 ADCLK cycles
A/D conversion
Sampling time
Disconnection detection assisting time (0 to 15 ADCLK cycles)
Conversion time
Sampling time
Disconnection detection assisting time (0 to 15 ADCLK cycles)
Conversion time