29. I2C Bus Interface (RIIC)
29.4
SCL Synchronization Circuit
In generation of the SCL (clock) signal, the RIIC starts counting out the value for width at high level specified in ICBRH
when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is
complete. When the RIIC detects the falling edge of the SCL0 line, it starts counting out the width at low level period
specified in ICBRL, and then stops driving the SCL0 line (releases the line) once counting of the width at low level is
complete. The SCL (clock) signal is thus generated.
If multiple master devices are connected to the I2C bus, a collision of SCL signals may arise due to contention with
another master device. In such cases, the master devices have to synchronize their SCL signals. Since this
synchronization of SCL signals must be bit by bit, the RIIC is equipped with a facility (the SCL synchronization circuit)
to obtain bit-by-bit synchronization of the SCL clock signals by monitoring the SCL0 line while in master mode.
When the RIIC has detected a rising edge on the SCL0 line and thus started counting out the width at high level specified
in ICBRH, and the level on the SCL0 line falls because an SCL signal is being generated by another master device, the
RIIC stops counting when it detects the falling edge, drives the level on the SCL0 line low, and starts counting out the
width at low level specified in ICBRL. When the RIIC finishes counting out the width at low level, it stops driving the
SCL0 line to the low level (i.e. releases the line). At this time, if the width at low level of the SCL clock signal from the
other master device is longer than the width at low level set in the RIIC, the width at low level of the SCL signal will be
extended. Once the width at low level for the other master device has ended, the SCL signal rises because the SCL line
has been released. When the RIIC finishes outputting the low-level period of the SCL clock of, the SCL0 line is released
and the SCL clock rises. That is, in cases of contention of SCL signals from more than one master, the width at high level
of the SCL signal is synchronized with that of the clock having the narrower width, and the width at low level of the SCL
signal is synchronized with that of the clock having the broader width. However, such synchronization of the SCL signal
is only enabled when the SCLE bit in ICFER is set to 1.
Figure 29.20
Generation and Synchronization of the SCL Signal from the RIIC
ICBRH
ICBRL
SCL0
ICBRL
ICBRH
ICBRL
SCL0
[SCL clock generation]
Compare match
(Counter clear, low-drive start)
ICBRH
ICBRL
Counter clear
ICBRH
ICBRL
ICBRH: I
2C bus bit rate high-level register (SCL clock high-level period counter)
ICBRL: I2C bus bit rate low-level register (SCL clock low-level period counter)
[SCL synchronization]
Rising of SCL detected
(High-level period count start)
Compare match
(Counter clear, SCL0 line released)
Falling of SCL detected
(Low-level period count start)
Low-level output of
other master device
Low-level output of
other master device