28. Serial Communications Interface (SCIc, SCId)
28.13.12 Limitation 2 on Usage of the Extended Serial Mode Control Section
An SCIc interrupt request is generated even if the extended serial mode is enabled. However, the SCIc interrupt should
not be used during reception of a start frame because SCId uses an SCIc interrupt request .
The two ways of dealing with this are described below. When a reception error is detected, clear the error flag of the SCIc
and initialize the control section of the SCId.
(1) Set the the SCR.RIE bit of the SCI (SCIc) to 1 to disable the output of interrupt requests. Check the error flags in the
SSR register for SCI? on completion of the reception of a start frame, because an ERI interrupt is not generated if a
reception error occurs. After reception of the start frame is completed, set the SCR.RIE bit of the SCIn to 1 by the
time the first byte of the information frame is received .
(2) Set the the SCR.RIE bit of the SCIn to 1 to disable RXI interrupts and enable ERI interrupts for ICUA.
Clear the IRn.IR flag to enable the acceptance of RXI interrupts by ICUA by the time the first byte of the
information frame is received after the completion of start frame reception.
Figure 28.72
Example of Flowchart for Reception Error Handling (During Reception of the Start Frame)
28.13.13 Points to Note on Starting Transfer
If the ICU.IRn.IR flag is 1 at the time transfer is to be started, an interrupt request is internally retained after transfer
starts, and this can lead to unanticipated behavior of the ICU.IRn.IR flag.
When the ICCR1.ICE bit is 1 at the time transfer is to start, follow the procedure below to clear interrupt requests before
enabling operations (by setting the SCR.TE or SCR.RE bit to 1).
(1) Confirm that transfer has stopped (i.e. that the SCR.TE and SCR.RE bits are 0).
(2) Clear the relevant interrupt enable bit (the SCR.TIE or SCR.RIE bit) to 0.
(3) Read the relevant interrupt enable bit (the SCR.TIE or SCR.RIE bit) and confirm that its value is 0.
(4) Clear the ICU.IRn.IR flag to 0.
Clear the ESMER.ESEM bit to 0
Clear the TCR.TCST bit to 0
Set the TMR.TOMS[1:0] bits
Disable extended serial functions. The state
of the control section is initialized.
Stop counting by the timer.
Set break field low period detection mode as the timer’s operating
mode.
Clear reception error flags for SCIn to 0
Set all bits in STCR to 1
Set the AEDIE, BCDIE, CF1MIE, CF0MIE and
BFDIE bits in the ICR.
Clear the reception error flags (ORER, FER and PER) in the SSR register for SCIc
to 0.
Clear all flags in the STR register.
Set interrupt enable bits as required.
Set the CR3.SDST bit to 1.
This starts detection of the start frame.
Set the ESMER.ESEM bit to 1
Enable extended serial functions.
Set the TCR.TCST bit to 1
Start counting by the timer so that judgment of break fields is possible .
Start of reception error handling
Completion of reception error handling
Set the TMR.TCSS[2:0] bits, and TPRE and TCNT
registers
Set a counter clock source that is suitable for the break field low period and set the
TPRE and TCNT registers.
*
1
Note1: The setting in this step is not necessary if the setting conditions
have not been changed.