REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
0.90
Aug. 09, 2011 26. Watchdog Timer (WDT)
846
Table 26.2 WDT Registers, changed
857
26.3.3 [Sample sequences of writing that are not valid for refreshing the counter]:
Description changed
27. Independent Watchdog Timer (IWDT)
864
Table 27.2 IWDT Registers, changed
876
27.3.3 [Sample sequences of writing that are not valid for refreshing the counter]:
Description changed
28. Serial Communications Interface (SCIc, SCId)
882, 883
Table 28.1 Specifications of SCIc, Table 28.1 Specifications of SCIc: Note deleted
883
Table 28.3 List of Functions of SCI Channels, changed
898
28.2.6 Serial Control Register (SCR): Description changed
907
28.2.8 Smart Card Mode Register (SCMR): Note added
925
28.2.16 SPI Mode Register (SPMR): Description changed
927
Table 28.22 Settings of the ESME Bits and Guaranteed Operation by Timer Operation Mode, added
929
28.2.20 Control Register 2 (CR2): Description changed
944
Figure 28.8 Sample SCI Initialization Flowchart (Asynchronous Mode), changed
946
Figure 28.10 Example of Serial Transmission Flowchart in Asynchronous Mode, changed
950
Figure 28.13 Example of Serial Reception Flowchart (2) (Asynchronous Mode), changed
952
Figure 28.15 Example of Multi-Processor Serial Transmission Flowchart, changed
957
28.5.2 CTS and RTS Functions: Description changed
958
Figure 28.20 Example of SCI Initialization Flowchart (Clock Synchronous Mode), changed
960
Figure 28.22 Example of Serial Transmission Flowchart (Clock Synchronous Mode): Note added
968
28.6.5 Initialization of the SCI (Smart Card Interface Mode): Description changed
981
Figure 28.43 Example of the Flow of SCI Initialization (for Simple I2C Mode): Description changed
987
28.8.1 States of Pins in Master and Slave Modes: Description changed
987
Table 28.25 States of Pins by Mode and Input Level on the SSn# Pin: Note added
1000
Figure 28.60 Example of Operations with Bus-Collision Detection, changed
1001
Figure 28.61 Example of Operations with the Digital Filter, changed
1002
Figure 28.63 Timing for Sampling of Data Received through RXDX12, changed
1012
28.12 Event Linking, changed
1018
28.13.10 External Clock Input in Clock Synchronous Mode, added
1019
28.13.12 Limitation 2 on Usage of the Extended Serial Mode Control Section: Description changed
1019
Figure 28.72 Example of Flowchart for Reception Error Handling (During Reception of the Start
Frame), added
29. I2C Bus Interface (RIIC)
1027,
1028
29.2.2 I2C Bus Control Register 2 (ICCR2): RSPA bit, added
—
29.16.2 Setting Input Buffer Control Register, deleted
30. Serial Peripheral Interface (RSPI)
1107
30.2.1 RSPI Control Register (SPCR): Description changed
1113 to
1115
30.2.5 RSPI Data Register (SPDR): Description changed
1114
Figure 30.3 Configuration of SPDR (Writing), added
1115
Figure 30.4 Configuration of SPDR (Reading), added
1119,
1120
30.2.9 RSPI Data Control Register (SPDCR): Description changed
1120
Table 30.5 Settable Combinations of SPSLN[2:0] Bits and SPFC[1:0] Bits, changed
1136 to
1140
30.3.4 Data Format: Description changed
1141 to
1144
30.3.5 Transfer Format: Description changed
1147
Figure 30.25 Operation Example of SPCR.TXMD = 0, changed
1148
Figure 30.26 Operation Example of SPCR.TXMD = 1, changed
1149
Figure 30.27 Operation Example of SPTI and SPRI Interrupts, changed
1152
Figure 30.28 Operation Example of OVRF Flag, changed
1154
Figure 30.29 Operation Example of PERF Flag, changed
1158
Figure 30.30 Procedure for Determining the Form of Serial Transmission in Master Mode, changed
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Summary