REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
0.90
Aug. 09, 2011
88
Table 2.14 Instructions that are Converted into Multiple Micro-Operations (multiplier: 32 × 32
64
bits), (memory source operand), added
3. Operating Modes
100
3.3.5 User Boot Mode, changed
5. I/O Registers
108
Table 5.1 List of I/O Registers (Address Order), SOSCWTCR, LOCOWTCR2, HOCOWTCR2,
added
114 to 116 Table 5.1 List of I/O Registers (Address Order): Interrupt source priority register, changed
6. Resets
131
Table 6.2 Targets to be Initialized by Each Reset Source, changed
139
6.3.3 Voltage Monitoring 1 Reset and Voltage Monitoring 2 Rese: Description changedt
140
Figure 6.2 Operation Examples During Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset,
added
141
6.3.5 Independent Watchdog Timer Reset: Description changed
141
6.3.6 Watchdog Timer Reset: Description changed
7. Initial Setting Memory
151
7.2.3 Endian Select Register B (MDEB), Endian Select Register S (MDES): Description changed
152
7.3 UB Code: Description changed
8. Voltage Detection Circuit (LVD)
156
Figure 8.2 Block Diagram of Voltage Monitoring 1 Interrupt/Reset Circuit, changed
157
Figure 8.3 Block Diagram of Voltage Monitoring 2 Interrupt/Reset Circuit, changed
159
8.2.1 Voltage Monitoring Circuit/Comparator A Control Register (LVCMPCR): Description changed
160
8.2.2 Voltage Detection Level Select Register (LVDLVLR): Description changed
161
8.2.3 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 0 (LVD1CR0):
Description changed
163
8.2.4 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 0 (LVD2CR0):
Description changed
165
8.2.5 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 1 (LVD1CR1):
Description changed
166
8.2.6 Voltage Monitoring 1 Circuit/Comparator A1 Status Register (LVD1SR): Description changed
167
8.2.7 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 1 (LVD2CR1):
Description changed
168
8.2.8 Voltage Monitoring 2 Circuit/Comparator A2 Status Register (LVD2SR): Description changed
169
8.3 VCC Input Voltage Monitor: Description changed
171
Table 8.4 Procedures for Setting Bits Related to the Voltage Monitor 1 Interrupt and Voltage Monitor
1 Reset, changed
172
Figure 8.5 Example of Voltage Monitoring 1 Interrupt Operation, changed
173
Table 8.5 Procedures for Setting Bits Related to the Voltage Monitor 2 Interrupt and Voltage Monitor
2 Reset, changed
174
Figure 8.6 Example of Voltage Monitoring 2 Interrupt Operation, changed
9. Clock Generation Circuit
176
Table 9.1 Specifications of Clock Generation Circuit, changed
179
9.2.1 System Clock Control Register (SCKCR): Description changed
183
9.2.4 PLL Control Register 2 (PLLCR2): Description changed
185
9.2.6 Main Clock Oscillator Control Register (MOSCCR): Description changed
186
9.2.7 Sub-Clock Oscillator Control Register (SOSCCR): Description changed
187
9.2.8 Low-Speed Clock Oscillator Control Register (LOCOCR): Description changed
188
9.2.9 IWDT-Dedicated Low-Speed Clock Oscillator Control Register (ILOCOCR):
Description changed
189
9.2.10 High-Speed Clock Oscillator Control Register (HOCOCR): Description changed
191
9.2.12 Oscillation Stop Detection Control Register (OSTDCR): Description changed
193
9.2.14 Main Clock Oscillator Forced Oscillation Control Register (MOFCR): Description changed
194
9.2.15 High-Speed Clock Oscillator Power Supply Control Register (HOCOPCR):
Description changed
196
9.3.3 Notes on the External Clock Input, added
198
9.4.2 Handling of Pins when Sub-Clock is Not Used: Description changed
200
Figure 9.8 Flow of Recovery from Detection of Oscillator Stop, added
200
9.5.2 Oscillation Stop Detection Interrupts: Description changed
204
9.10.1 Notes on Clock Generation Circuit: Description changed
205
9.10.5 Notes on Sub-Clock, changed
Rev.
Date
Description
Page
Summary