11. Low Power Consumption
11.6.2
All-Module Clock Stop Mode
11.6.2.1
Transition to All-Module Clock Stop Mode
After setting the MSTPCRA.ACSE bit to 1 and placing modules controlled by MSTPCRA, MSTPCRB, and MSTPCRC
registers in the module stop state (MSTPCRA = FFFF
FF[C-F]Fh*1, MSTPCRB = FFFF FFFFh, MSTPCRC[31:16] =
FFFFh), executing a WAIT instruction while the SBYCR.SSBY bit is 0 stops the bus controller, I/O ports, and all
modules except for the 8-bit timer
s*2, IWDT, RTCA, power-on reset circuit, voltage detection circuit at the end of the
current bus cycle, and the chip enters all-module clock stop m
ode*3.When the WDT is used, the WDT stops counting when all-module clock stop mode is entered.
Counting by the IWDT stops if a transition to all-module clock-stop mode is made while the IWDT is being used in auto-
start mode and the OFS0.IWDTSLCSTP bit is 1. In the same way, counting by the IWDT stops if a transition to all-
module clock-stop mode is made while the IWDT is being used in register start mode and the SLCSTP bit in
IWDTCSTPR is 1.
Furthermore, counting by the IWDT continues if a transition to all-module clock-stop mode is made while the IWDT is
being used in auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by the IWDT continues through transitions
to low-power-consumption modes). In the same way, counting by the IWDT continues if a transition to all-module clock-
stop mode is made while the IWDT is being used in register start mode and the SLCSTP bit in IWDTCSTPR is 0.
To use all-module clock-stop mode, make the following settings and then execute a WAIT instruction.
(1) Clear the PSW.I bit
*4 of the CPU to 0.
(2) Set the interrupt destination to be used for recovery from all-module clock stop mode to the CPU.
(3) Set the
priority*5 of the interrupt to be used for recovery from all-module clock stop mode to a level higher than the
setting of the PSW.IPL[3:0] bits
*4 of the CPU.
(4) Set the IERm.IENj bit
*5 for the interrupt to be used for recovery from all-module clock stop mode to 1.
(5) For the last I/O register to which writing proceeded, read the register to confirm that the value written has been
reflected.
(6) Execute a WAIT instruction (executing a WAIT instruction causes automatic setting of the PSW.I
bit*4 of the CPU
to 1).
Note 1.
When the MSTPA15 or MSTPA14 bit in MSTPCRA is set, all-module clock stop mode can be entered even
while the module is in operation state. However, the transition to all-module clock stop mode should be made in
stopped state.
Note 2.
The MSTPCRA.MSTPA4 and MSTPA5 bits select operation or stop of these modules.
Note 3.
Transitions to all-module clock stop mode are not to be made in some states of DTC or DMACA operations.
Before setting the MSTPCRA.MSTPA28 bit to 1, clear the DMAST.DMST bit of the DMACA and the
DTCST.DTCST bit of the DTC so that the DTC and DMACA are not activated.
Note 4.
Note 5.