30. Serial Peripheral Interface (RSPI)
SPCMDm register is used to set a transfer format for the RSPI in master mode. Each channel has eight RSPI command
registers (SPCMD0 to SPCMD7). Some of the bits in SPCMD0 register is used to set a transfer mode for the RSPI in
slave mode. The RSPI in master mode sequentially references SPCMDm register according to the settings in the
SPSCR.SPSLN[2:0] bits, and executes the serial transfer that is set in the referenced SPCMDm register.
SPCMDm register should be set while the transmit buffer is empty (data for the next transfer is not set) and before setting
of the data that is to be transmitted when that SPCMDm register is referenced.
SPCMDm that is referenced by the RSPI in master mode can be checked by means of the SPSSR.SPCP[2:0] bits. If the
contents of SPCMDm are changed while the SPCR.MSTR bit is 0 and the SPCR.SPE bit is 1, subsequent operations
cannot be guaranteed.
CPHA Bit (RSPCK Phase Setting)
The CPHA bit sets an RSPCK phase of the RSPI in master mode or slave mode. Data communications between RSPI
modules require the same RSPCK phase setting between the modules.
CPOL Bit (RSPCK Polarity Setting)
The CPOL bit sets an RSPCK polarity of the RSPI in master mode or slave mode. Data communications between RSPI
modules require the same RSPCK polarity setting between the modules.
BRDV[1:0] Bits (Bit Rate Division Setting)
The BRDV[1:0] bits are used to determine the bit rate. A bit rate is determined by combinations of the settings in the
the base bit rate. The settings in the BRDV[1:0] bits are used to select a bit rate which is obtained by dividing the base bit
rate by 1, 2, 4, or 8. In SPCMDm register, different BRDV[1:0] bit settings can be specified. This permits the execution
of serial transfers at a different bit rate for each command.
SSLA[2:0] Bits (SSL Signal Assertion Setting)
The SSLA[2:0] bits control the SSLAi signal assertion when the RSPI performs serial transfers in master mode.
Setting the SSLA[2:0] bits controls the assertion for the SSLAi signal. When an SSLAi signal is asserted, its polarity is
determined by the set value in the corresponding SSLP. When the SSLA[2:0] bits are set to 000b in multi-master mode,
serial transfers are performed with all the SLL signals in the negated state (as the SSLA0 pin acts as input).
When using the RSPI in slave mode, set the SSLA[2:0] bits to 000b.
SSLKP Bit (SSL Signal Level Keeping)
When the RSPI in master mode performs a serial transfer, the SSLKP bit specifies whether the SSLAi signal level for the
current command is to be kept or negated between the SSL negation timing associated with the current command and the
SSL assertion timing associated with the next command.
When using the RSPI in slave mode, the SSLKP bit should be set to 0.