REVISION HISTORY
Under development Preliminary document
Specifications in this document are tentative and subject to change.
0.90
Aug. 09, 2011 10. Clock Frequency Accuracy Measurement Circuit (CAC)
208
10.2.1 CAC Control Register 0 (CACR0): Description changed
11. Low Power Consumption
All in this
section
Mode name, changed: Middle-speed operating mode 1,2
Middle-speed operating mode A,B
SOSCWTCR,LOCOWTCR2, HOCOWTCR2 register, added
222
Table 11.3 List of Registers Related to Low Power Consumption Functions, changed
224
11.2.1 Standby Control Register (SBYCR): Description changed
230 to 232 11.2.5 Normal Operating Power Consumption Control Register (NMPCCR): Description changed
233
11.2.6 Sleep Mode Return Clock Source Switching Register (RSTCKCR): Description changed
234
11.2.7 Main Clock Oscillator Wait Control Register (MOSCWTCR): Description changed
235
11.2.8 Sub-Clock Oscillator Wait Control Register (SOSCWTCR), added
236
11.2.9 PLL Wait Control Register (PLLWTCR): Description changed
237
11.2.10 LOCO Wait Control Register 2 (LOCOWTCR2), added
238
11.2.11 HOCO Wait Control Register 2 (HOCOWTCR2), added
239
11.2.12 Deep Standby Control Register (DPSBYCR): Description changed
242
11.2.14 Deep Standby Interrupt Enable Register 2 (DPSIER2): Description changed
248
11.2.19 Flash HOCO Sofware Standby Control Register (FHSSBYCR): Description changed
252
11.6.1.1 Transition to Sleep Mode: Description changed
253
11.6.1.3 Sleep Mode Return Clock Source Switching Function: Description changed
254
11.6.2.1 Transition to All-Module Clock Stop Mode: Description changed
255
11.6.2.2 Canceling All-Module Clock Stop Mode: Description changed
256
11.6.3.1 Transition to Software Standby Mode: Description changed
257
11.6.3.2 Canceling Software Standby Mode: Description changed
260
11.6.4.2 Canceling Deep Software Standby Mode: Description changed
263
Figure 11.4 Example of Flowchart to Use Deep Software Standby Mode, changed
264
11.7.7 Rewrite the Register by DMACA and DTC in Sleep Mode, added
12. Register Write Protection Function
265
Table 12.1 Correspondences between PRCR Bits and Registers to be Protected, changed
14. Interrupt Control Unit (ICUA)
All in this
section
Terms, changed:
Low power-voltage detection 1 → Voltage-monitoring 1 interrupt
Low power-voltage detection 2 → Voltage-monitoring 2 interrupt
Low Power-Voltage Detection 1 Status Flag → Voltage-Monitoring 1 Interrupt Status Flag
Low Power-Voltage Detection 2 Status Flag → Voltage-Monitoring 2 Interrupt Status Flag
Low Power-Voltage Detection 1 Enable Bit → Voltage-Monitoring 1 Interrupt Enable Bit
Low Power-Voltage Detection 2 Enable Bit → Voltage-Monitoring 2 Interrupt Enable Bit
293
14.2.8 IRQ Control Register i (IRQCRi) (i = 0 to 7): Description changed
310
Table 14.4 Interrupt Vector Table: Note 2. deleted
322
14.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt, added
15. Buses
326
Table 15.2 Addresses Assigned for Each Bus, changed
331
Table 15.5 Specifications of the External Bus, changed
332
15.2.7 Bus Settings: Description changed
335
15.3.1 CSn Control Register (CSnCR) (n = 0 to 3): Description changed
348, 349
15.3.6 CSn Wait Control Register 2 (CSnWCR2) (n = 0 to 3): Description changed
385
Table 15.12 Types of Bus Errors, changed
16. DMA Controller (DMACA)
394
16.2.4 DMA Block Transfer Count Register (DMCRB): Description changed
412
16.3.2 Extended Repeat Area Function: Description changed
420
Table 16.8 DMACA Execution Cycles: Note 1. added
17. Data Transfer Controller (DTC)
434
17.2.2 DTC Mode Register B (MRB): Description changed
438
17.2.6 DTC Transfer Count Register B (CRB): Description changed
442
17.3 Sources of Activation: Description changed
445
Figure 17.4 Operation Flowchart of the DTC, changed
454
Figure 17.9 Example (1) of DTC Operation Timing, changed
454
Figure 17.10 Example (2) of DTC Operation Timing, changed
455
Figure 17.11 Example (3) of DTC Operation Timing, changed
455
Figure 17.12 Example (4) of DTC Operation Timing, changed
Rev.
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Description
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Summary