参数资料
型号: W631GG6KB-12
厂商: Winbond Electronics
文件页数: 140/159页
文件大小: 0K
描述: IC DDR3 SDRAM 1GBIT 96WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR3 SDRAM
存储容量: 1G(64M x 16)
速度: 800MHz
接口: 并联
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 85°C
封装/外壳: 96-TFBGA
供应商设备封装: 96-WBGA(9x13)
包装: 托盘
W631GG6KB
AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
PARAMETER
DDR3-1866 (-11)
MIN.
MAX.
UNITS NOTES
Command and Address Timing
t DLLK
t RTP
t WTR
DLL locking time
Internal READ Command to PRECHARGE
Command delay
Delay from start of internal write transaction to
internal read command
512
max(4nCK, 7.5nS)
max(4nCK, 7.5nS)
?
?
?
nCK
8
8, 26
t WR
t MRD
t MOD
t CCD
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
15
4
max(12nCK, 15nS)
4
?
?
?
?
nS
nCK
nCK
8, 26
t DAL (min)
Auto precharge write recovery + precharge time
WR + roundup(t RP (min)/ t CK (avg))
nCK
6
t MPRR
t RRD
t FAW
Multi-Purpose Register Recovery Time
ACTIVE to ACTIVE command period for 2KB page
size
Four activate window for 2KB page size
1
max(4nCK, 6nS)
35
?
?
?
nCK
nS
29
8
8
t IS(AC135)
t IS(AC125)
t IH(DC100)
Command and Address
setup time to CK, CK#
Command and Address
setup time to CK, CK#
Command and Address
hold time from CK, CK#
Base specification
V REF @ 1 V/nS
Base specification
V REF @ 1 V/nS
Base specification
V REF @ 1 V/nS
65
200
150
275
100
200
pS
pS
pS
pS
pS
pS
9, 41
9, 41, 42
9, 41
9, 41, 42
9, 41
9, 41, 42
t IPW
Control and Address input pulse width for each
input
535
?
pS
10
Calibration Timing
t ZQ init
t ZQ oper
Power-up and RESET calibration time
Normal operation Full calibration time
max(512nCK, 640nS)
max(256nCK, 320nS)
?
?
t ZQCS
Normal operation Short calibration time
max(64nCK, 80nS)
?
33
Reset Timing
t XPR
Exit Reset from CKE HIGH to a valid command
max(5nCK, 120nS)
?
Self Refresh Timing
t XS
Exit Self Refresh to commands not requiring a
locked DLL
max(5nCK, 120nS)
?
34
t XSDLL
t CKESR
t CKSRE
t CKSRX
Exit Self Refresh to commands requiring a locked
DLL
Minimum CKE low width for Self Refresh entry to
exit timing
Valid Clock Requirement after Self Refresh Entry
(SRE)
Valid Clock Requirement before Self Refresh Exit
(SRX)
t DLLK (min)
t CKE (min) + 1nCK
max(5 nCK, 10nS)
max(5 nCK, 10nS)
?
?
?
?
nCK
35
Refresh Timing
t RFC
REF command to ACT or REF command time
110
?
nS
36
t REFI
Average periodic
refresh Interval
0°C ≤ T CASE ≤ 85°C
85°C < T CASE ≤ 95°C
?
?
7.8
3.9
μ S
μ S
Publication Release Date: Dec. 09, 2013
Revision A05
- 140 -
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