参数资料
| 型号： | W631GG6KB-12 |
| 厂商： | Winbond Electronics |
| 文件页数： | 69/159页 |
| 文件大小： | 0K |
| 描述： | IC DDR3 SDRAM 1GBIT 96WBGA |
| 标准包装： | 200 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR3 SDRAM |
| 存储容量： | 1G（64M x 16） |
| 速度： | 800MHz |
| 接口： | 并联 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 96-TFBGA |
| 供应商设备封装： | 96-WBGA（9x13） |
| 包装： | 托盘 |
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W631GG6KB
8.17 Power-Down Modes
8.17.1 Power-Down Entry and Exit
Power-down is synchronously entered when CKE is registered low (along with NOP or Deselect
command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL
operations, DLL locking or read / write operation are in progress. CKE is allowed to go low while any
of other operations such as row activation, precharge or auto-precharge and refresh are in progress,
but power-down I DD spec will not be applied until finishing those operations. Timing diagrams are
shown in Figure 59 through Figure 71 with details for entry and exit of Power-Down.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode
for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC
timing and voltage specification as well as proper DLL operation with any CKE intensive operations as
long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in-progress commands are completed, the
device will be in precharge Power-Down mode; if any bank is open after in-progress commands are
completed, the device will be in active Power-Down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, CKE and
RESET#. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or
Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are
defined as t CPDED . CKE_low will result in deactivation of command and address receivers after t CPDED
has expired.
Table 7 – Power-Down Entry Definitions
Status of DRAM
Active
(A bank or more Open)
Precharged
(All banks Precharged)
Precharged
(All banks Precharged)
MRS bit A12
Don't Care
0
1
DLL
On
Off
On
PD Exit
Fast
Slow
Fast
Relevant Parameters
tXP to any valid command
tXP to any valid command. Since it is in precharge state,
commands here will be ACT, REF, MRS, PRE or PREA.
tXPDLL to commands that need the DLL to operate, such
as RD, RDA or ODT control line.
tXP to any valid command
Also, the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept
enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode,
CKE low, RESET# high, and a stable clock signal must be maintained at the inputs of the DDR3
SDRAM, and ODT should be in a valid state, but all other input signa ls are ―D on't Care .‖ (If RESET#
goes low during Power-Down, the DRAM will be out of PD mode and into reset state.) CKE low must
be maintained until t CKE has been satisfied. Power-down duration is limited by 9 times t REFI of the
device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or
Deselect command). CKE high must be maintained until t CKE has been satisfied. A valid, executable
command can be applied with power-down exit latency, t XP and/or t XPDLL after CKE goes high. Power-
down exit latency is defined in section 10.16 “ AC Characteristics ” on page 138.
Active Power Down Entry and Exit timing diagram example is shown in Figure 59. Timing Diagrams
for CKE with PD Entry, PD Exit with Read and Read with Auto Precharge, Write, Write with Auto
Precharge, Activate, Precharge, Refresh, and MRS are shown in Figure 60 through Figure 68.
Additional clarifications are shown in Figure 69 through Figure 71.
Publication Release Date: Dec. 09, 2013
Revision A05
- 69 -
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| W632 | 制造商:LUMINIS 制造商全称:LUMINIS 功能描述:Wall mount |
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