参数资料
型号: W631GG6KB-12
厂商: Winbond Electronics
文件页数: 54/159页
文件大小: 0K
描述: IC DDR3 SDRAM 1GBIT 96WBGA
标准包装: 200
格式 - 存储器: RAM
存储器类型: DDR3 SDRAM
存储容量: 1G(64M x 16)
速度: 800MHz
接口: 并联
电源电压: 1.425 V ~ 1.575 V
工作温度: 0°C ~ 85°C
封装/外壳: 96-TFBGA
供应商设备封装: 96-WBGA(9x13)
包装: 托盘
W631GG6KB
8.13.2.6 Burst Read Operation followed by a Precharge
The minimum external Read command to Precharge command spacing to the same bank is equal to AL + t RTP with t RTP being the Internal Read
Command to Precharge Command Delay. Note that the minimum ACT to PRE timing, t RAS.MIN must be satisfied as well. The minimum value for the
Internal Read Command to Precharge Command Delay is given by t RTP.MIN = max(4 × nCK, 7.5 nS). A new bank active command may be issued to the
same bank if the following two conditions are satisfied simultaneously:
1. The minimum RAS precharge time (t RP.MIN ) has been satisfied from the clock at which the precharge begins.
2. The minimum RAS cycle time (t RC.MIN ) from the previous bank activation has been satisfied.
Examples of Read commands followed by Precharge are show in Figure 38 and Figure 39.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
Command
NOP
READ
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
NOP
Address
Bank a,
Col n
t RTP
Bank a,
(or all)
t RP
Bank a,
Row b
RL = AL + CL = 9
DQS, DQS#
BL4 Operation:
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
DQS, DQS#
BL8 Operation:
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
NOTES: 1. RL = 9 (CL = 9, AL = 0)
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes t RAS.MIN is satisfied at Precharge command time (T5) and that t RC.MIN is satisfied at the next Active command time (T14).
TRANSITIONING DATA
DON'T CARE
Figure 38 – READ to PRECHARGE (RL = 9, AL = 0, CL = 9, t RTP = 4, t RP = 9)
Publication Release Date: Dec. 09, 2013
Revision A05
- 54 -
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