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参数资料
型号： W631GG6KB-12
厂商： Winbond Electronics
文件页数： 7/159页
文件大小： 0K
描述： IC DDR3 SDRAM 1GBIT 96WBGA
标准包装： 200
格式 - 存储器： RAM
存储器类型： DDR3 SDRAM
存储容量： 1G（64M x 16）
速度： 800MHz
接口： 并联
电源电压： 1.425 V ~ 1.575 V
工作温度： 0°C ~ 85°C
封装/外壳： 96-TFBGA
供应商设备封装： 96-WBGA（9x13）
包装： 托盘
W631GG6KB
4. KEY PARAMETERS
Speed Bin
DDR3-1866
DDR3-1600
DDR3-1333
CL-nRCD-nRP
Part Number Extension
13-13-13
-11
11-11-11 9-9-9
- 12/12I/12A/12 K - 15/15I/15A/15 K
Unit
Parameter
Sym.
Min.
Max.
Min.
Max.
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
f CKMAX
t AA
t RCD
t RP
t RC
t RAS
?
13.91
13.91
13.91
47.91
34
933
20
?
?
?
9 * t REFI
?
13.75
(13.125) 7
13.75
(13.125) 7
13.75
(13.125) 7
48.75
(48.125) 7
35
800
20
?
?
?
9 * t REFI
?
13.5
(13.125) 7
13.5
(13.125) 7
13.5
(13.125) 7
49.5
(49.125) 7
36
667
20
?
?
?
9 * t REFI
MHz
nS
nS
nS
nS
nS
CL = 6
CWL = 5
t CK(AVG)
2.5
3.3
2.5
3.3
2.5
3.3
nS
CL = 7
CWL = 6
t CK(AVG)
Reserved
1.875
<2.5
1.875
<2.5
nS
CL = 8
CWL = 6
t CK(AVG)
1.875
<2.5
1.875
<2.5
1.875
<2.5
nS
CL = 9
CWL = 7
t CK(AVG)
Reserved
1.5
<1.875
1.5
<1.875
nS
CL = 10
CWL = 7
t CK(AVG)
1.5
<1.875
1.5
<1.875
1.5
<1.875
nS
CL = 11
CWL = 8
t CK(AVG)
Reserved
1.25
<1.5
Reserved
nS
CL = 13
CWL = 9
t CK(AVG)
1.07
<1.25
Reserved
Reserved
nS
Supported CL Settings
Supported CWL Settings
Sup_CL
Sup_CWL
6, 8, 10, 13
5, 6, 7, 9
6, (7) , 8, (9) , 10, 11
5, 6, 7, 8
6, (7) , 8, 9, 10
5, 6, 7
nCK
nCK
-40°C ≤ T CASE ≤ 85°C
?
? * 2
?
7.8 * 2, 3
?
7.8 * 2, 3
μ S
Average periodic
refresh Interval
0°C ≤ T CASE ≤ 85°C
85°C < T CASE ≤ 95°C
t REFI
?
?
7.8 *
3.9 *
1
4
?
?
7.8 *
3.9 *
1
4
?
?
7.8 * 1
3.9 * 4
μ S
μ S
95°C < T CASE ≤ 105°C
?
? *
6
?
3.9 *
5, 6
?
3.9 * 5, 6
μ S
Operating One Bank Active-Precharge Current
Operating One Bank Active-Read-Precharge
Current
Operating Burst Read Current
Operating Burst Write Current
Burst Refresh Current
Self-Refresh Current, T OPER = 0 ~ 85°C
Operating Bank Interleave Current
I DD0
I DD1
I DD4R
I DD4W
I DD5B
I DD6
I DD7
?
?
?
?
?
?
?
130
165
330
260
185
14
430
?
?
?
?
?
?
?
115
145
280
220
170
14
400
?
?
?
?
?
?
?
105
130
240
190
160
14
380
mA
mA
mA
mA
mA
mA
mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤ T CASE ≤ 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤ T CASE < 0°C is not available.
3. 12I, 12A, 12K, 15I, 15A and 15K speed grades support -40°C ≤ T CASE ≤ 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, T CASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( t REFI = 3.9 μS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0 b and MR2 A7 = 1 b ) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1 b , MR2 A7 is don't care).
5. For 12K and 15K automotive parts, T CASE is able to extend to 105°C with doubling Auto Refresh commands in frequency to a
32 mS period ( t REFI = 3.9 μS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0 b and MR2 A7 = 1 b ) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1 b , MR2 A7 is
don't care).
6. For -11, -12, 12I, 12A, -15, 15I and 15A speed grade parts, 95°C < T CASE ≤ 105°C is not available.
7. For devices supporting optional down binning to CL=7 and CL=9, t AA /t RCD /t RP min must be 13.125 nS or lower. SPD settings
must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)
should program 13.125 nS in SPD bytes for t AA min (Byte 16), t RCD min (Byte 18), and t RP min (Byte 20). DDR3-1600 (11-11-11)
devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for
t AA min (Byte16), t RCD min (Byte 18), and t RP min (Byte 20). Once t RP (Byte 20) is programmed to 13.125 nS, t RC min (Byte 21,
23) also should be programmed accodingly. For example, 49.125nS (t RAS min + t RP min = 36 nS + 13.125 nS) for DDR3-1333
(9-9-9) and 48.125 nS (t RAS min + t RP min = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
Publication Release Date: Dec. 09, 2013
Revision A05
-7-
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