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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 102/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
Datasheet
Intel Wireless Flash Memory (W18)
07-Dec-2005
Order Number: 290701, Revision: 015
95
2.
Illegal commands are those not defined in the command set.
3.
All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in
undermined data when a partition address is read.
4.
Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to different partitions,
the second write determines the active partition. Both partitions will output status information when read.
5.
If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Intel devices.
6.
The Clear Status command clears Status Register error bits except when the WSM is running (Pgm Busy, Erase Busy,
Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In
Erase Suspend).
7.
EFP writes are allowed only when Status Register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm
command. Any other commands are treated as data.
8.
The "current state" is that of the WSM, not the partition.
9.
Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then
move to the Ready State.
10.
In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block", and "CR
Write". Both cycles of other two cycle commands ("OEM CAM program & confirm", "Program OTP & confirm", "EFP Setup
& confirm", "Erase setup & confirm") will be ignored. In Program suspend or Program suspend in Erase suspend, both
cycles of all two cycle commands will be ignored.
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