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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 6/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
Datasheet
Intel Wireless Flash Memory (W18)
07-Dec-2005
Order Number: 290701, Revision: 015
103
Table 45.
Partition Region 1 Information
Offset
(1)
See table below
P = 39h
Description
Address
Bottom
Top
(Optional flash features and commands)
Len
Bot
Top
(P+1A)h
(P+1A)h Number of identical partitions within the partition region
2
53:
(P+1B)h
54:
(P+1C)h
1
55:
(P+1D)h
1
56:
(P+1E)h
1
57:
(P+1F)h
1
58:
(P+20)h
(P+20)h Partition Region 1 Erase Block Type 1 Information
4
59:
(P+21)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
5A:
(P+22)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
5B:
(P+23)h
5C:
(P+24)h
(P+24)h Partition 1 (Erase Block Type 1)
25D:
5D:
(P+25)h
Minimum block erase cycles x 1000
5E:
(P+26)h
1
5F:
(P+27)h
1
60:
(P+28)h
Partition Region 1 Erase Block Type 2 Information
4
61:
(P+29)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
62:
(P+2A)h
bits 16–31 = z, region erase block(s) size are z x 256 bytes
63:
(P+2B)h
(bottom parameter device only)
64:
(P+2C)h
Partition 1 (Erase block Type 2)
2
65:
(P+2D)h
Minimum block erase cycles x 1000
66:
(P+2E)h
167:
(P+2F)h
168:
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
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