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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 20/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
20
Order Number: 290701, Revision: 015
4.2
Signal Descriptions
the QUAD+ package.
Table 5.
Signal Descriptions - VF BGA Package
Symbol
Type
Name and Function
A[22:0]
Input
ADDRESS INPUTS: For memory addresses. 32-Mbit: A[20:0]; 64-Mbit: A[21:0]; 128-Mbit: A[22:0]
D[15:0]
Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
ADV#
Input
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or the next valid CLK edge with
ADV# low, whichever occurs first.
CE#
Input
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and places all outputs in High-Z.
CLK
Input
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or the next valid CLK edge with ADV# low, whichever occurs first.
OE#
Input
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
RST#
Input
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
WAIT
Output
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to
be asserted-high or asserted-low based on bit 10 of the Read Configuration Register. WAIT is tri-
stated if CE# is deasserted. WAIT is not gated by OE#.
WE#
Input
WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the
rising edge of WE#.
WP#
Input
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 13.1, “Block Lock Operations” on page 77 for details on block locking.
VPP
Power
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP
voltages should not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
VCC
Power
DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC
voltages should not be attempted.
VCCQ
Power
OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly
to VCC.
VSS
Power
GROUND: Pins for all internal device circuitry must be connected to system ground.
VSSQ
Power
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
DU
—
DO NOT USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
NC
—
NO CONNECT: No internal connection; can be driven or floated.
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