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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 99/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
92
Order Number: 290701, Revision: 015
14.9
Burst Wrap (RCR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst-
length boundary or whether they cross word-length boundaries to perform linear accesses. No-
wrap mode (RCR[3]=1) enables WAIT to hold off the system processor, as it does in the
continuous burst mode, until valid data is available. In no-wrap mode (RCR[3]=0), the device
operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-
word bursts.
For example, if RCR[3]=0 (wrap mode) and RCR[2:0] = 1h (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If RCR[3]=1 (no-wrap mode) and RCR[2:0] = 1h (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR[3]=1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting RCR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst
sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for
example, consumes power during the initial access, again during the internal pipeline lookup as the
processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the device pipelines the next 4-word sequence. RCR[3]=1 while in 4-word burst mode
(no-wrap mode) reduces this excess power consumption.
14.10
Burst Length (RCR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in synchronous read
access of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous
word.
Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see
Table 33, “Sequence and Burst Length” on page 91). When a burst cycle begins, the device outputs
synchronous burst data until it reaches the end of the “burstable” address space.
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