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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 97/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
90
Order Number: 290701, Revision: 015
Note:
WAIT shown asserted high (RCR[10]=1).
14.6
WAIT Delay (RCR[8])
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be
asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-, 8-, 16-, or continuous-word
burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary
(16-word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur.
If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read
sequence. The WAIT signal informs the system of this delay.
14.7
Burst Sequence (RCR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 33, “Sequence and
Burst Length” on page 91). When operating in a linear burst mode, either 4-, 8-, or 16-word burst
length with the burst wrap bit (RCR[3]) set, or in continuous burst mode, the device may incur an
output delay when the burst sequence crosses the first 16-word boundary. (See Figure 37, “Word
Boundary” on page 86 for word boundary description.) This depends on the starting address. If the
starting address is aligned to a 4-word boundary, there is no delay. If the starting address is the end
of a 4-word boundary, the output delay is one clock cycle less than the First Access Latency Count;
this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses
a 16-word boundary. The WAIT pin informs the system of this delay. For timing diagrams of WAIT
functionality, see these figures:
Figure 39.
Data Output Configuration with WAIT Signal Delay
DQ
15-0 [Q]
CLK [C]
Valid
Output
Valid
Output
Valid
Output
DQ
15-0 [Q]
Valid
Output
1 CLK
Data Hold
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
t
CHQV
t
CHQV
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
2 CLK
Data Hold
t
CHTL/H
Note 1
Valid
Output
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