参数资料
型号: PH28F128W18BD60A
厂商: INTEL CORP
元件分类: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封装: 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件页数: 94/106页
文件大小: 1496K
代理商: PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
88
Order Number: 290701, Revision: 015
14.3
WAIT Signal Polarity (RCR[10])
If the WAIT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. This means
that a 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data.
Conversely, if RCR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted,
then data is ready and valid. WAIT is asserted during asynchronous page mode reads.
14.4
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT
signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 12, “WAIT
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an “asserted” state as determined by RCR[10]. See Figure 8, “Page-Mode Read
From a system perspective, the WAIT signal is in the asserted state (based on RCR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or if the device is operating in asynchronous mode (RCR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity of what is appearing on the data bus.
Figure 38.
Example: Latency Count Setting at 3
A
MAX-0 (A)
DQ
15-0 (D/Q)
CLK (C)
CE# (E)
ADV# (V)
R103
Valid
Output
Valid
Output
High Z
t
ADD-DELAY
t
DATA
1nd
0st
2rd
3th
4th
Valid Address
Code 3
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