- 您现在的位置：买卖IC网 > PDF目录296802 > PH28F128W18BD60A (INTEL CORP) 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 PDF资料下载
参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 75/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页当前第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页
Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
70
Order Number: 290701, Revision: 015
Figure 27.
Enhanced Factory Program Flowchart
EFP Setup
EFP Program
EFP Verify
EFP Exit
1. WA
0 = first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur , the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal to
WA
terminates the EFP verify phase, and instructs the device to exit EFP
.
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
Comments
Bus
State
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
See the Full Status Check procedure in the
Word Program flowchart.
Write
Standby
Read
Write
(note 2)
Read
Standby
Write
Read
Standby
EFP
Setup
Program
Done?
Exit
Program
Phase
Last
Data?
Exit
Verify
Phase
EFP
Exited?
Write
EFP
Confirm
Read
Standby
EFP
Setup
Done?
Read
Standby
Verify
Stream
Ready?
Write
Unlock
Block
Write
(note 1)
Standby
Last
Data?
Standby
(note 3)
Verify
Done?
S
R
[0
]=1
=
N
Write Data
Address = WA
0
Last
Data?
Write FFFFh
Address
≠ BBA
Program
Done?
Read
Status Register
SR[0]=0=Y
Y
S
R
[0
]=1
=
N
Write Data
Address = WA
0
Verify
Done?
Last
Data?
Read
Status Register
Write FFFFh
Address
≠ BBA
Y
Verify Stream
Ready?
Read
Status Register
SR[7]=0=N
Full Status Check
Procedure
Operation
Complete
Read
Status Register
EFP
Exited?
SR[7]=1=Y
SR[0]=1=N
Start
Write 30h
Address = WA
0
V
PP = 12V
Unlock Block
Write D0h
Address = WA
0
EFP Setup
Done?
Read
Status Register
SR[7]=1=N
Exit
N
EFP Program
EFP Verify
EFP Exit
EFP Setup
ENHANCED FACTORY PROGRAMMING PROCEDURE
Comments
Bus
State
Data = 30h
Address = WA
0
Data = D0h
Address = WA
0
Status Register
Check SR[7]
0 =
EFP ready
1 =
EFP not ready
V
PP = 12V
Unlock block
Check SR[0]
0 = Program done
1 = Program not done
Status Register
Data = FFFFh
Address not within same
BBA
Data = Data to program
Address = WA
0
Device automatically
increments address.
Comments
Bus
State
Data = Word to verify
Address = WA
0
Status Register
Device automatically
increments address.
Data = FFFFh
Address not within same
BBA
Status Register
Check SR[0]
0 = Ready for verify
1 = Not ready for verify
Check SR[0]
0 = Verify done
1 = Verify not done
Status Register
Check SR[7]
0 = Exit not finished
1 = Exit completed
Check V
PP & Lock
errors (SR[3,1])
Data Stream
Ready?
Read
Status Register
SR[0] =0=Y
S
R
[7
]=0
=
Y
SR[0]=1=N
Standby
Read
Data
Stream
Ready?
Check SR[0]
0 = Ready for data
1 = Not ready for data
Status Register
SR[0]=0=Y
SR[0] =0=Y
EFP setup time
Standby
EFP setup time
Standby
Error
Condition
Check
If SR[7] = 1:
Check SR[3,1]
SR[3] = 1 = V
PP error
SR[1] = 1 = locked block
相关PDF资料 |
PDF描述 |
|---|---|
| PHC0683E1133-H | IC SOCKET |
| PHP12NQ15T | N-channel TrenchMOS transistor |
| PHB12NQ15T | N-channel TrenchMOS transistor |
| PHD12NQ15T | N-channel TrenchMOS transistor |
| PHP15N06E | PowerMOS transistor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PH28F160C3BD70A | 制造商:Micron Technology Inc 功能描述:MM#865392FLASH 28F160C3BD 70 VF-PBGA46 C |
| PH28F256L18B85 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| PH28F256L18B85A | 制造商:Micron Technology Inc 功能描述:MM#875138FLASH 28F256L18B 85 VF-PBGA79 S |
| PH28F256L18T85 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| PH28F320C3TD70A | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 3V/3.3V 32M-Bit 2M x 16 70ns 48-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:MM#869664FLASH 28F320C3TD 70 VF-PBGA47 E |
发布紧急采购，3分钟左右您将得到回复。