参数资料
型号: PH28F128W18BD60A
厂商: INTEL CORP
元件分类: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封装: 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件页数: 5/106页
文件大小: 1496K
代理商: PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
102
Order Number: 290701, Revision: 015
Table 43.
Burst Read Information for Non-muxed Device
Table 44.
Partition and Erase-block Region Information
Table 42.
Protection Register Information
Offset
P = 39h
Lengt
h
Description
(Optional Flash Features and Commands)
Add.
Hex
Code
Value
(P + E)h
1
Number of Protectuib Register fields in JEDEC ID space.
“00h” indicates that 256 protection fields are available.
47:
--01
1
(P + E)h
(P + 10)h
(P + 11)h
(P + 12)h
4
Protection Field 1: Protection Description
This field describes user-available One Time
Programmable (OTP) Protection Register bytes, Some
are pre-programmed with device-unique serial numbers.
Others are user-programmable. Bits are 0-15 point to the
Protection Register lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-
programmable:
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bites 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
48:
49:
4A:
4B:
--80
--00
--03
80h
00h
8 byte
Offset
(1)
Length
Description
Hex
P = 39h
(Optional flash features and commands)
Add.
Code Value
(P+13)h
1
4C:
--03
8 byte
(P+14)h
1
4D:
--04
4
(P+15)h
1
4E:
--01
4
(P+16)h
1
Synchronous mode read capability configuration 2
4F:
--02
8
(P+17)h
1
Synchronous mode read capability configuration 3
50:
--03
16
(P+18)h
1
Synchronous mode read capability configuration 4
51:
--07
Cont
Page Mode Read capability
bits 0–7 = “n” such that 2
n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2
n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Offset
(1)
See table below
P = 39h
Description
Address
Bottom
Top
(Optional flash features and commands)
Len
Bot
Top
(P+19)h
1
52:
Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
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