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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 66/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
62
Order Number: 290701, Revision: 015
10.5
CFI Query
This device contains a separate CFI query database that acts as an “on-chip datasheet.” The CFI
information within this device can be accessed by issuing the Read Query command and supplying
a specific address. The address is constructed from the base address of a partition plus a particular
offset corresponding to the desired CFI field. Appendix B, “Common Flash Interface (CFI)” on
page 96 shows accessible CFI fields and their address offsets.
Issuing the Read Query command to a partition that is programming or erasing puts that partition in
read query mode while the partition continues to program or erase in the background.
10.6
Read Status Register
The device’s Status Register displays program and erase operation status. A partition’s status can
be read after writing the Read Status Register command to any location within the partition’s
address range. Read-status mode is the default read mode following a Program, Erase, or Lock
Block command sequence. Subsequent single reads from that partition will return its status until
another valid command is written.
The read-status mode supports single synchronous and single asynchronous reads only; it doesn’t
support burst reads. The first falling edge of OE# or CE# latches and updates Status Register data.
The operation doesn’t affect other partitions’ modes. Because the Status Register is 8 bits wide,
only DQ [7:0] contains valid Status Register data; DQ [15:8] contains zeros. See Table 22, “Status
Each 4-Mbit partition contains its own Status Register. Bits SR[6:0] are unique to each partition,
but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides
program and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit,
SR[0], provides program and erase status of the addressed partition only. Status register bits
SR[6:1] present information about partition-specific program, erase, suspend, VPP, and block-lock
presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Protection Register Lock Status
Partition
80h
Lock Data
Protection Register
Partition
81h - 88h
Register Data
Multiple reads required to read
the entire 128-bit Protection
Register.
Notes:
1.
The address is constructed from a base address plus an offset. For example, to read the Block Lock
Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e.
0F8002h. Then examine bit 0 of the data to determine if the block is locked.
2.
See Section 13.1.4, “Block Lock Status” on page 79 for valid lock status.
Table 21.
Device Identification Codes (Sheet 2 of 2)
Item
Address1
Data
Description
Base
Offset
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