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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 11/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
12
Order Number: 290701, Revision: 015
The Command User Interface (CUI) is the system processor’s link to internal flash memory
operation. A valid command sequence written to the CUI initiates device Write State Machine
(WSM) operation that automatically executes the algorithms, timings, and verifications necessary
to manage flash memory program and erase. An internal Status Register provides ready/busy
indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST# – can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal Status
Registers, and provides an additional level of flash write protection.
2.1
Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or
RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The
device’s memory array is asymmetrically blocked, which enables system code and data integration
within a single flash device. Each block can be erased independently in block erase mode.
Simultaneous program and erase operations are not allowed; only one partition at a time can be
actively programming or erasing. See Table 1, “Bottom Parameter Memory Map” on page 13 and
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
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