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参数资料
| 型号： | PH28F128W18BD60A |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56 |
| 封装： | 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56 |
| 文件页数： | 71/106页 |
| 文件大小： | 1496K |
| 代理商： | PH28F128W18BD60A |
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Intel
Wireless Flash Memory (W18)
Datasheet
Intel Wireless Flash Memory (W18)
07-Dec-2005
Order Number: 290701, Revision: 015
67
The 12-V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use.12 V may be
Ratings and Operating Conditions” on page 24. VPP may be connected to 12 V for a total of tPPH
hours maximum. Stressing the device beyond these limits may cause permanent damage.
11.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements
to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm
eliminates the traditional overhead delays of the conventional word program mode in both the host
programming system and the flash device. Changes to the conventional word programming
flowchart and internal WSM routine were developed because of today's beat-rate-sensitive
manufacturing environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the device and checks the Status Register to determine when
the data has completed programming. This modification essentially cuts write bus cycles in half.
Following each internal program pulse, the WSM increments the device's address to the next
physical location. Now, programming equipment can sequentially stream program data throughout
an entire block without having to setup and present each new address. In combination, these
enhancements reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this, PROM
programmers can rely on the device to verify that it has been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 27, “Enhanced
Factory Program Flowchart” on page 70 for a detailed graphical representation of how to
implement EFP.
11.3.1
EFP Requirements and Considerations
EFP Requirements
Ambient temperature: TA = 25 °C ± 5 °C
VCC within specified operating range
VPP within specified VPP2 range
Target block unlocked
EFP Considerations
Block cycling below 100 erase cycles
1
RWW not supported2
EFP programs one block at a time
EFP cannot be suspended
Notes:
1.
Recommended for optimum performance. Some degradation in performance may
occur if this limit is exceeded, but the internal algorithm will continue to work
properly.
2.
Code or data cannot be read from another partition during EFP.
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